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Visitor snovak
Registered: ‎02-20-2017

create_generate_clock not able to find correct pin eventhough get_pins by itself is successful

I have a relatively simply simple clock divider circuit where I can divide an incoming clock by an arbitrary programmable integer value. This clock divider module is under the top level and its instance name is u_clk_div. The resulting clock divided output comes out on the port CLK_OUT I create a clock on the main incoming clock: create_clock -period 9.920 -name IncomingClk [get_ports InClk] and then attempt to create a generated clock using the following command: create_generated_clock -name dut_clk -source [get_ports InClk] -divide_by 6 [get_pins u_clk_div/CLK_OUT] I have verified that I have no typos and that my heirarchy is correct by using the tcl query interface % get_pins -hierarchical */CLK_OUT u_spin_clk_div/CLK_OUT I check when I synthesize that the top level module is indeed what I expect. The warning I am getting is WARNING: [Vivado 12-508] No pins matched 'u_clk_div/CLK_OUT'. Do I need to explicitely state what my working module is in my *.xdc file? I think the pin name and hier is correct so I am guessing Vivado is confused what the working top level module is? (Eventhough the correct top level module is highlighted when I am synthesizing) .
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Registered: ‎01-16-2013

Re: create_generate_clock not able to find correct pin eventhough get_pins by itself is successful


So when you query for pins % get_pins -hierarchical */CLK_OUT
I guess you got u_spin_clk_div/CLK_OUT

But in your command it is [get_pins u_clk_div/CLK_OUT] so please cross check once again.

Apart from the above syntax issue, I have one more suggestions.
From your description looks like you are developing the RTL to divide clock so it's ultimately become fabric generated clock.
Fabric generated clocks are not recommended design practice in FPGA. This have high clock skew and noise issues.

You can use the PLL/MMCM to generate divide by 6 clock.

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