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suzuki-run
Newbie
Newbie
328 Views
Registered: ‎04-07-2021

critical warning in spartan7

Hi all,

I want to fix this critical warning.

[Timing 38-194] Unsupported spread-spectrum parallel clocking configuration found between CLK66M and CLK_OUT1_CLKGEN_20M3. Timing analysis will be inaccurate!
Resolution: If the logic between the 2 clock domains needs to be timed, then the spread-spectrum clocking configuration should be removed from both CMBs.
If the logic between the 2 clock domains does not need to be timed, then an exclusive clock group can be defined between the 2 clocks domains:
set_clock_groups -group [get_clocks source_clock_domain] -group [get_clocks destination_clock_domain] -logically_exclusive


These nets CLK66M and CLK_OUT1_CLKGEN_20M3, CLK66M exists on the XDC file, but strangely CLK_OUT1_CLKGEN_20M3 does not exist.

Of course, if add constrain net CLK_OUT1_CLKGEN_20M3, a No valid pbjects error will occur.

So far, I know the details of Net CLK_OUT1_CLKGEN_20M3 are as follows.
[U_CLKGEN/M_CLKGEN_20M3/inst/CLK_OUT1_CLKGEN_20M3]

Why does Net CLK_OUT1_CLKGEN_20M3 get a critical warning? How can I resolve this critical warning?

Thank you and regards.

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13 Replies
hongh
Moderator
Moderator
291 Views
Registered: ‎11-04-2010

Have you tried to separate the clocks with set_clock_groups command suggested in the CW and handle the CDC path with logical method?

Ex: set_clock_groups -group [get_clocks CLK66M ] -group [get_clocks -of [get_pins U_CLKGEN/M_CLKGEN_20M3/inst/CLK_OUT1_CLKGEN_20M3]] -logically_exclusive

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suzuki-run
Newbie
Newbie
286 Views
Registered: ‎04-07-2021

Dear hongh

Thank you very much for your quick responce.

I tryed that method.

However, as I wrote in the question, "No valid objects" occur at the time of implementation.

This "No valid objects" is occurring for "CLK_OUT1_CLKGEN_20M3".

Thank you for your continued support.

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hongh
Moderator
Moderator
281 Views
Registered: ‎11-04-2010

What's the command your are using? "get_clocks CLK_OUT1_CLKGEN_20M3" or "get_nets CLK_OUT1_CLKGEN_20M3" ?

Have you tried the command I provided? 

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suzuki-run
Newbie
Newbie
254 Views
Registered: ‎04-07-2021

Dear hongh

I tryed two constraint methods.

First below,
create_clock -period 50.000 -name CO1_20M -waveform {0.000 25.000} -add [get_nets U_CLKGEN/M_CLKGEN_20M3/inst/CLK_OUT1_CLKGEN_20M3]
set_clock_groups -group [get_clocks CLK66M] -group [get_clocks CO1_20M] -logically_exclusive


Next below,
set_false_path -from [get_clocks CLK66M] -to [get_pins U_CLKGEN/M_CLKGEN_20M3/inst/CLK_OUT1_CLKGEN_20M3]

However, in both cases, No valid objects have occurred.
See the attached file for details.

regards

trial2.png
trial1.png
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suzuki-run
Newbie
Newbie
237 Views
Registered: ‎04-07-2021

added attachfile

critical_warning.png
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hongh
Moderator
Moderator
233 Views
Registered: ‎11-04-2010

Could you provide your synthesized dcp?

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suzuki-run
Newbie
Newbie
224 Views
Registered: ‎04-07-2021

Is the top DCP file in the hierarchy okay?

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suzuki-run
Newbie
Newbie
215 Views
Registered: ‎04-07-2021

I send top of dcp file.

(I couldn't attach it as it was, so I compressed it.)

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hongh
Moderator
Moderator
187 Views
Registered: ‎11-04-2010

Hi, @suzuki-run ,

Please upload the complete dcp with Ezmove link sent to you.

For MMCM/PLL in the design, please create clock on the input pin of MMCM/PLL and the tool will derive output clock automatically. 

 

 

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watari
Teacher
Teacher
176 Views
Registered: ‎06-16-2013

Hi @suzuki-run 

 

Did you try to disable spread spectrum on CLK66M ?

If no, would you try it ?

As you may know, EDA tool can't calculate proper waveform during STA stage.

 

Hope this helps.

 

Best regards,

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suzuki-run
Newbie
Newbie
168 Views
Registered: ‎04-07-2021

I know that, But I absolutery need spread spectrum.

I'm sorry to have taken the trouble.

Thank you

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hongh
Moderator
Moderator
161 Views
Registered: ‎11-04-2010

Ex:

set_clock_groups -group [get_clocks CLK66M] -group [get_clocks -of [get_pins U_CLKGEN/M_CLKGEN_20M3/inst/CLK_OUT1]]  -logically_exclusive

 

For MMCM/PLL in the design, please create clock on the input pin of MMCM/PLL and the tool will derive output clock automatically. 

 

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suzuki-run
Newbie
Newbie
67 Views
Registered: ‎04-07-2021

Dear hongh,

I will try to use report clock interaction.

Thank you

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