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alangford
Participant
Participant
1,646 Views
Registered: ‎06-15-2017

critical warning with IO location constraints

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Hi,

 

Tool: Vivado 2017.2

Devboard: zc706 with Zynq-7000 xcz7045

 

My design uses 2 Aurora lanes which Ive had working for some time. My pin constraints for the MGTs are taken directly from the datasheet for the devboard.

 

For no apparent reason, I opened the project today and it failed to place due to illegal location constraints

 

See the attached screenshot for details

 

The tool is reporting that the site locations in my xcf are not valid. In the pin planner, the pins I have constraints for the Aurora TX lanes are reported as unavailable. Although the details for these pins (V1/V2/Y1/Y2) are correct, i.e. MGTXTX#, OPAD, the ports available to select are the Aurora RX data inputs. 

 

For some reason the tool seems to think these pins have already been assigned. It is then attempting to place my Aurora TX lanes at different sites (AE20/AD20/AB20/AB19)

 

Ive blown out the .runs directory but this makes no difference.

 

The exact codebase was building just fine yesterday. 

 

Any suggestions what may be going on?

 

Thanks!

io_constraints_issue.jpg
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alangford
Participant
Participant
2,330 Views
Registered: ‎06-15-2017

Hi both,

 

I found the cause of my problem ... no surprise, it was an error on my part!

 

I have my Aurora logic inside a generate statement to allow me to optionally build without it. I had forgotten that the last time I worked with this project I had set the generic to build the Aurora logic to FALSE. This fits with why the tool was able to place the RX serial lines but not the TX lines.

 

Although it makes sense how the tool was handling this problem, it was really confusing me until I realised that the GTX IP wasnt actually present in my design.

 

Thanks for your replies. 

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thakurr
Moderator
Moderator
1,616 Views
Registered: ‎09-15-2016

Hi @alangford

 

Are you seeing same issue in other Vivado versions especially the latest version 2017.3? Can you share the opt dcp for further debugging?

Try running the below commands in the tcl console for implementation and see if it helps ?

opt_design

place_ports

place_deisgn

route_design

 

Regards

Rohit

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Regards
Rohit
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syedz
Moderator
Moderator
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Registered: ‎01-16-2013

@alangford,

 

The exact codebase was building just fine yesterday.

 

Vivado should always give repeatable results. Can you please recheck if you have made any changes to design?

Can you please try recreating the project? 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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syedz
Moderator
Moderator
1,581 Views
Registered: ‎01-16-2013

@alangford,

 

Did you overcome the error after recreating the project? If the issue still exists then please share the post routed dcp file.

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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alangford
Participant
Participant
2,331 Views
Registered: ‎06-15-2017

Hi both,

 

I found the cause of my problem ... no surprise, it was an error on my part!

 

I have my Aurora logic inside a generate statement to allow me to optionally build without it. I had forgotten that the last time I worked with this project I had set the generic to build the Aurora logic to FALSE. This fits with why the tool was able to place the RX serial lines but not the TX lines.

 

Although it makes sense how the tool was handling this problem, it was really confusing me until I realised that the GTX IP wasnt actually present in my design.

 

Thanks for your replies. 

View solution in original post

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