design hierarchy and constraints

[interqos]

Hi,

When we apply the constraints on the low-level module, a SDRAM controller, both offset_in and offset_out constraints can take effect. When we apply the constraint of the top module, only the offset-out constraint can take effect. How can we apply the constraint correctly?

FYI, our target device is V6 and our ISE version is 12.4. My company is in Hong Kong. Can I contact the FAE in China by phone?

Thanks,

Ronald

[debrajr]

Check if you have set Keep Heirarchy as Yes in Synthesis Properties. Once done open the netlist and apply the constraints accordingly.