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Explorer
Explorer
19,037 Views
Registered: ‎01-15-2008

divider generator 3.0 problem with Virtex 6

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Hi all,

I have a design which I'm migrating from Virtex5 (SX50T) to Virtex6 (CX130T).  I've been bogged down for several days over the fact that the design takes about 10 hours to map, where it used to take 30 min in the old device (though the new one is 4x bigger).  I've narrowed it down to the following:

I have a divider core generated with Divider Generator v3.0.  I regenerated the core for the V6, but when MAP gets to phase 10.8 it just hangs up.  This is true even when I instantiate just thedivider and nothing else.  Divider Generator 3.0 is supposed to support V6, but something is wrong.

I could use Divder Generator v4.0 I suppose, but the ports are all different.

 

Any ideas appreciated.

 

Thanks,

 

Rick

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Explorer
Explorer
21,789 Views
Registered: ‎01-15-2008

Re: divider generator 3.0 problem with Virtex 6

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I discovered the problem here.  The 10-hour mapping occurs when I used Divider Generator 3.0 with the Virtex6 device IF I selected the Radix-2, 1 clock per result, implementation.  If I changed to either "High Radix" or 2 clocks per result, the mapping finished in a minute.

Hope that helps somebody else.

 

Rick

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27 Replies
Explorer
Explorer
21,790 Views
Registered: ‎01-15-2008

Re: divider generator 3.0 problem with Virtex 6

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I discovered the problem here.  The 10-hour mapping occurs when I used Divider Generator 3.0 with the Virtex6 device IF I selected the Radix-2, 1 clock per result, implementation.  If I changed to either "High Radix" or 2 clocks per result, the mapping finished in a minute.

Hope that helps somebody else.

 

Rick

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Visitor franchute
Visitor
19,005 Views
Registered: ‎04-26-2012

Re: divider generator 3.0 problem with Virtex 6

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I know this post is old, but I needed to thank you for solving it. I've been trying to solve this for days. I even wrote again my modules sharing only 1 divider to see if that could be mapped by the ISE.

 

I'm working with a Spartan6 , so for Spartan6 user this post is valid to!

 

Thnx
Regards

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Historian
Historian
18,971 Views
Registered: ‎02-25-2008

Re: divider generator 3.0 problem with Virtex 6

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@rikraf wrote:

I discovered the problem here.  The 10-hour mapping occurs when I used Divider Generator 3.0 with the Virtex6 device IF I selected the Radix-2, 1 clock per result, implementation.  If I changed to either "High Radix" or 2 clocks per result, the mapping finished in a minute.

Hope that helps somebody else.

 

Rick


Sounds like it was trying to fit a large combinatorial block and make it meet timing. Adding the second register pipelined the divider, so the tools are more easily able to make it work.

----------------------------Yes, I do this for a living.
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Explorer
Explorer
18,718 Views
Registered: ‎02-27-2008

Re: divider generator 3.0 problem with Virtex 6

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I've run into the same problem.  A Divider Generator 3.0 that worked on a Virtex 5 took > 10 hours to map on a Virtex 6.  I'm running ISE 13.2.  Divider settings: radix2, 32 bit dividend/quotient, 16 bit divisor, 16 bit fractional remainder, unsigned, 1 clock per division.  I verified this bug by instantiating the divider alone in a fresh XC6VLX75T project.  Divider Generator 4.0 has the same problem.  Switching to 2 clocks per division fixes it (but breaks my exisiting designs).  I'm downloading ISE 14.2 now to see if the bug still exists.

 

-Greg

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Explorer
Explorer
18,710 Views
Registered: ‎02-27-2008

Re: divider generator 3.0 problem with Virtex 6

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The bug still exists in ISE 14.2. Changing the target device to a Virtex 5 also solves the problem. I've opened a web case to try to squash this particular bug.
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Explorer
Explorer
18,669 Views
Registered: ‎02-27-2008

Re: divider generator 3.0 problem with Virtex 6

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The result of the webcase was that this is indeed a bug in the tools.  It's been flagged to be corrected in a future ISE version.

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Visitor ben.marshall
Visitor
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Registered: ‎02-26-2013

Re: divider generator 3.0 problem with Virtex 6

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Does anyone know if this bug has been fixed?

 

I've tested ISE 14.5 and it still seems to exist.

 

Regards,

Ben

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Explorer
Explorer
17,828 Views
Registered: ‎02-27-2008

Re: divider generator 3.0 problem with Virtex 6

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I don't think it has been corrected. I just did a test with ISE 14.6 and Divider Generator 4.0 on a V6, and it still hangs. Vivado 2013.2 with Divider Generator 5.0 on a K7 implements successfully, but that doesn't help you. Good luck, it would be nice for this bug to be fixed! Maybe open another web case?

In the interim, I've been using the Hardware Division Unit core at opencores.org. It's not identical, but was close enough for my uses.

-Greg
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Visitor ben.marshall
Visitor
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Registered: ‎02-26-2013

Re: divider generator 3.0 problem with Virtex 6

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I've been contacted by Xilinx to say that this is still an outstanding bug in ISE, inlcuding 14.6.

 

My solution at the moment is to use Vivado HLS to generate a System Generator IP block for a fixed point division.

 

This goes through map in a matter of minutes not hours.

 

Equally HLS could be used to generate VHDL/Verilog for use in a standard design, i.e. without going down the System Generator route.

 

Ben

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Newbie jeffpages
Newbie
9,327 Views
Registered: ‎09-13-2013

Re: divider generator 3.0 problem with Virtex 6

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One of my S6 projects has always taken 10 to 12 hours to map, but after seeing this thread I went and checked, and sure enough, it's using the divider with radix-2 1 clock per result. I changed it to 2 clocks per result (fortunately I had enough spare cycles to accomodate this) and it now maps in minutes!

 

Jeff

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Observer ilansousa
Observer
9,268 Views
Registered: ‎11-04-2011

Re: divider generator 3.0 problem with Virtex 6

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Hi,

and what about in ISE 14.7, does anybody knows if this problem has been fixed in this newer version? I am asking, because my design needs one result per clock cycle, therefore configuring it to "Clocks per division">1 will not obey the constraints in my design.

Currently I'm using ISE 14.6, and I would like to know before updating to this 14.7.

Thanks in advance.

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Participant ucabsdp
Participant
9,189 Views
Registered: ‎07-06-2013

Re: divider generator 3.0 problem with Virtex 6

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To my expereince this problem still exists in ISE 14.7, I am creating a design for the Zynq-7020 and am experincing 48hr+ mapping times when using dividers with CPD = 1.

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Visitor rchakraborty
Visitor
9,020 Views
Registered: ‎06-14-2012

Re: divider generator 3.0 problem with Virtex 6

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Hello rikraf,
I have run into this issue in ISE 14.5 and thanks to this post, I know where to look as I have divider in my sysgen design.
However, when I was grappling with issue, I could not come up with a concrete debug plan to identify the problem.

I am very interested to know how you narrowed it down to the divider? What files did you look at to zero in on the divider? What was you debug strategy?

Thank you very much

Rohit
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Visitor ben.marshall
Visitor
9,011 Views
Registered: ‎02-26-2013

Re: divider generator 3.0 problem with Virtex 6

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Rohit,

 

I might be able to help you out wth this. I narrowed it down to the divider because I put the design through map/place and route at serveral points during the development phase in order to get accurate resource usage figures. I was therfore able to notice the build time had increased a vast amount and look at what had recently been put into the design.

 

I then proceeded to put a divider with the same settings as in my design into a testbench on it's own. This gave the same symptoms. t this point I googled around and found this post and spoke to the XIlinx Support team who confirmed the bug,

 

As far as I know this issue hasn't ben fixed yet. As discussed in previous posts one solution is to use a divider that does not provide an output on every clock cycle. If you absolutely require the full throughput rate (I did) then I see the two main options as to either use two identical divide cores each with the half rate throughput. Or the option I took which is to use Vivado HLS to generate a divide core which can then be imported to sysgen. This proved to be an easy enough task.

 

Good luck!

 

Ben

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Explorer
Explorer
9,004 Views
Registered: ‎01-15-2008

Re: divider generator 3.0 problem with Virtex 6

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I found the problem the brute-force way:  I had a working design in an earlier version of the tools, after upgrade the mapping took forever, so I just started removing things to see when it sped up.  Not elegant, but it got me there.

 

Rick

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Visitor rchakraborty
Visitor
8,979 Views
Registered: ‎06-14-2012

Re: divider generator 3.0 problem with Virtex 6

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Thank you Ben
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Visitor rchakraborty
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8,979 Views
Registered: ‎06-14-2012

Re: divider generator 3.0 problem with Virtex 6

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Thank you Rick!
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Visitor hbaier
Visitor
7,831 Views
Registered: ‎11-22-2008

Re: divider generator 3.0 problem with Virtex 6

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Thanks a lot.

 

I have the same proble with a zynq device, I try to fix it by importing the ise design to Vivado.

 

It is really sad, that xilinx does not inform its customers about this problem.

 

Heinz

 

 

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Visitor hbaier
Visitor
7,815 Views
Registered: ‎11-22-2008

Re: divider generator 3.0 problem with Virtex 6

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Hi Ben,

could you spend a minute and describe in a few sentences how you did this, like

 

1. generate the divider under vivado 

2. start sysgen  ?? is sysgen a stand alone tool ?

2.1 install sysgen ???

3. start sysgen ...

4. import file  divider.??  

5. output of sysgen ... ?

6. use file ??   in ISE

 

Thanks

Heinz

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Xilinx Employee
Xilinx Employee
6,924 Views
Registered: ‎02-06-2013

Re: divider generator 3.0 problem with Virtex 6

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Hi

 

You cannot use vivado if your target  device is virtex6.

 

The only workaround for 5 and 6 series devices is to use the clock per division option other than 1.

 

As this issue is seen only when the clocks per division option is set to 1 in the divider core.

 

Refer below links for more details about system generator and design with this tool

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug897-vivado-sysgen-user.pdf

Regards,

Satish

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Visitor hbaier
Visitor
6,915 Views
Registered: ‎11-22-2008

Re: divider generator 3.0 problem with Virtex 6

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Thanks, my device is zynq
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Visitor ben.marshall
Visitor
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Registered: ‎02-26-2013

Re: divider generator 3.0 problem with Virtex 6

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hbair,

 

If your using the Zynq then you will have to use Vivado. This bug has been fixed in Vivado so you should be able to generate and use any divider you want!

 

Ben

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Visitor hbaier
Visitor
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Registered: ‎11-22-2008

Re: divider generator 3.0 problem with Virtex 6

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Thanks a lot, but right know I use ISE 14.7 with Zynq xc7z045
very successful. PCIE dma, a lot of image processing/filters,
I started importing the project into Vivado, that will take me a while.
Problems in Vivado started with the download cable :(,
So for the short term I would have liked to continue with ISE, but with the divder generated in Vivado.
Anyway, this all helped me a lot.
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Observer moberg
Observer
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Registered: ‎10-18-2013

Re: divider generator 3.0 problem with Virtex 6

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This bug hanged my mapping in 14.7.

 

The design is for a zynq. Will this ever be fixed or is the bug dropped?

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Visitor hbaier
Visitor
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Registered: ‎11-22-2008

Re: divider generator 3.0 problem with Virtex 6

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Mine hang too,  try to set the map  Placer Effort Level to standard.  That helped me. I took 3 hours to map, 

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Xilinx Employee
Xilinx Employee
6,744 Views
Registered: ‎06-14-2012

Re: divider generator 3.0 problem with Virtex 6

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Currently the focus is to fix issues in Vivado. Hence there is a lot of push for Vivado adoption.

But please feel free to let us know if design hangs in ISE and there is no switch that helps workaround this.

 

We will be glad to help.

 

Regards

Sikta

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Xilinx Employee
Xilinx Employee
6,734 Views
Registered: ‎02-06-2013

Re: divider generator 3.0 problem with Virtex 6

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Hi

 

This is not yet fixed for ISE,the workaround is to use clock per division value set to values other than 1.

Regards,

Satish

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