11-10-2013 07:17 AM
I am building a 2x2 MIMO filter on virtex-5.
I am using the following three options in xst
1. enable hierarchy --- for post-rote simulation to add signals to wave window
2. LUT combining --- auto (saw synthesis tutorial video on xilinx site and enabled these two)
3. reduce control sets- auto
without the first option set to yes, map gives a failure saying there are not enough slices to map your design
This is the exact error message I am getting.
Phase 15.9 Local Placement Optimization
ERROR:Place:543 - This design does not fit into the number of slices available
in this device due to the complexity of the design and/or constraints.
Unplaced instances by type:
DSP48E 7 (6.3)
Please evaluate the following:
- If there are user-defined constraints or area groups:
Please look at the "User-defined constraints" section below to determine
what constraints might be impacting the fitting of this design.
Evaluate if they can be moved, removed or resized to allow for fitting.
Verify that they do not overlap or conflict with clock region restrictions.
See the clock region reports in the MAP log file (*map) for more details
on clock region usage.
- If there is difficulty in placing LUTs:
Try using the MAP LUT Combining Option (map lc area|auto|off).
- If there is difficulty in placing FFs:
Evaluate the number and configuration of the control sets in your design.
instances that failed to place:
0. Placer RPM "Dsp" (size: 7)
ERROR:Place:120 - There were not enough sites to place all selected components.
Some of these failures can be circumvented by using an alternate algorithm
(though it may take longer run time). If you would like to enable this
algorithm please set the environment variable XIL_PAR_ENABLE_LEGALIZER to 1
and try again
The following instances are the last set of Phase 15.9 Local Placement Optimization (Checksum:f79ff752) REAL time: 1 mins 29 secs
Total REAL time to Placer completion: 1 mins 29 secs
Total CPU time to Placer completion: 1 mins 23 secs
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
See MAP report file "channel_emulator_map.mrp" for details.
Problem encountered during the packing phase.
Number of errors : 3
Number of warnings : 18
Process "Map" failed
How do I trace this back and get the design to map before this option ? I was not using this option initially.
I added it just to confirm my post-route simulation since I found very difficult to add internal signals without this option.
Can there be a bigger problem in my design since it works only with this option ??
I know I am using only 87% of the DSP blocks, 112 out of 128 but why is this error coming I cannot understand.
For reference, I am attaching synthesis report with this post.
Thanks and Regards,
11-10-2013 08:26 AM
There is a clue in this message... "0. Placer RPM "Dsp" (size: 7)". I think this is indicating that there is a complex function in your design that is built using 7 DSP48 cells, presumably using the cascade paths between them. Since they are using the cascade paths, they must be placed in a bunch of 7 DSP contiguous cells in the same column.
So, while you are only using 112 of the 128 DSP cells in the design, by the time the placer gets to placing this function (RPM means Relatively Placed Macro, or something like that), it no longer has 7 consecutive DSPs available.
This is your classic "backpack packing" problem (look it up on Wikipedia). You have a number of objects of different sizes, and you need to fit them into the finite resource of the FPGA. If the packing is done perfectly, then maybe you can use all 128 of the 128 DSP slices available, but if the packing is imperfect, you won't be able to get it to fit. If you ever covered this in a computer algorithms, this is a classicly known NP-complete problem. (Ironically, my 2nd post of the day that mentions NP-complete problems).
Even though the input space here is relatively small (I don't know how many DSP RPMs there are in your design), one of the attributes of NP-complete problems is that the search space grows exponentially in the number of inputs. So even with only 128 DSP48 locations in the device, this is not going to be solved by an exhaustive search that is guaranteed to find the "best" packing of the RPMs into the DSP columns, it is going to be solved with heuristics. As a result, it isn't guaranteed to find the best solution.
From your previous runs, you know that a solution exists (it found one in the past), but you changed "something" and now it has found a different local minimum, in which the best solution the heuristics can find don't fit.
Again, I don't know how many large RPMs of DSP48 cells you have. If you only have a couple, then you could try manually LOCating them. By doing this, you force the tools to place the larger ones in known locations first, and then it can place the smaller ones around them. However, if you have a large number of larger RPMs, this is going to be very challenging...
11-11-2013 07:28 AM
I'd just add the following to Avrum's post:
It's possible that this is simply a random starter placement error. So it may just be luck that the design fit with the map settings you used. I would suggest one of two paths if you want to use different map settings than the ones that worked:
1) Use the DSP placements (generate LOC constraints based on the existing placement) from the working version. Then presumably you can change the map settings and not run into this particular error again.
2) After setting up map the way you want, run SmartXplorer over a range of starting cost table values to find a (potentially different) workable placement.
11-11-2013 05:57 PM
I'll move it to Implementation board as it's a placer issue.
02-23-2014 04:05 AM
i'm using xilinx ise 12.1 version.i want to change all the d flipflops used in synthesis to master slave d flipflop.is it possible to change the basic components used in synthesis?please help me