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Newbie
Newbie
3,414 Views
Registered: ‎02-05-2010

emulating open faults

Hello. Good day to everyone.

 

we are currently doing a project on an FPGA based BIST using Spartan 3E starter kit and the Xilinx as our medium. Part of our objective is to test for open faults in our circuit. We were wondering where or during what stage would it be easier for us to emulate open faults in our circuit?

 

We would appreciate your helpful response to our dire need. Thank you! =)

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Historian
Historian
3,396 Views
Registered: ‎02-25-2008

Re: emulating open faults


marislim wrote:

Hello. Good day to everyone.

 

we are currently doing a project on an FPGA based BIST using Spartan 3E starter kit and the Xilinx as our medium. Part of our objective is to test for open faults in our circuit. We were wondering where or during what stage would it be easier for us to emulate open faults in our circuit?

 

We would appreciate your helpful response to our dire need. Thank you! =)


Etiquette tells us that you should not post the same question in EVERY SINGLE FORUM.

Jeez.

----------------------------Yes, I do this for a living.
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