UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Participant a4speaker
Participant
5,682 Views
Registered: ‎08-16-2011

error: clockplacer not placing GTP clocks properly

I need to verify aurora simplex cores loopback on AC701 board.

Design is as shown in attached diagram.

My TOP file has folowing conections

 

output    TXP,
output    TXN, 
input      reset,             // active high. from SW8 on board
input      GTPQ0_P,    // gt ref clk.125 Mhz from ICS844021 IC
input      GTPQ0_N,
input      RXP,
input      RXN,
output    CLK_MUX_SEL0,
output    CLK_MUX_SEL1

 

for loopback, TXP and TXN should go SMA connectors on board and connected to RXP and RXN SMA connectors.

 

When i implement design, i get following error

 

[Place 30-511] Unroutable Placement! A GTPE_COMMON / GTPE_CHANNEL clock component pair is not placed in a routable site pair. The GTPE_COMMON component can use the dedicated path between the GTPE_COMMON and the GTPE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the CELL.NETs used in this clock placement rule is listed below. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets AURORA_RX_TOP/aurora_module_i/gt_common_support/gt0_pll0outclk_i] >

AURORA_RX_TOP/aurora_module_i/gt_common_support/gtpe2_common_0_i (GTPE2_COMMON.PLL0OUTCLK) is provisionally placed by clockplacer on GTPE2_COMMON_X1Y0
AURORA_RX_TOP/aurora_module_i/aurora_8b10b_rx_i/inst/gt_wrapper_i/aurora_8b10b_rx_multi_gt_i/gt0_aurora_8b10b_rx_i/gtpe2_i (GTPE2_CHANNEL.PLL0CLK) is provisionally placed by clockplacer on GTPE2_CHANNEL_X0Y2

The above error could possibly be related to other connected instances. Following is a list of 
all the related clock rules and their respective instances.

Clock Rule: rule_bufds_mmcm
Status: FAIL 
Rule Description: A BUFDS driving an MMCM must both be in the same clock region
AURORA_RX_TOP/aurora_module_i/IBUFDS_GTE2_CLK1 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y0
AURORA_RX_TOP/aurora_module_i/INIT_CLOCK_GEN_RX/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y1
ERROR: The above is also an illegal clock rule
Workaround: < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets AURORA_RX_TOP/aurora_module_i/gt_refclk1_i] >

Clock Rule: rule_bufds_gtp_common_intelligent_pin
Status: PASS 
Rule Description: A BUFDS driving a GTPCommon must both be placed in the same or adjacent clock region
(top/bottom)
AURORA_RX_TOP/aurora_module_i/IBUFDS_GTE2_CLK1 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y0
AURORA_RX_TOP/aurora_module_i/gt_common_support/gtpe2_common_0_i (GTPE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTPE2_COMMON_X1Y0

Clock Rule: rule_mmcm_bufg
Status: PASS 
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
AURORA_RX_TOP/aurora_module_i/INIT_CLOCK_GEN_RX/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X0Y1
AURORA_RX_TOP/aurora_module_i/INIT_CLOCK_GEN_RX/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y3

Clock Rule: rule_mmcm_bufg
Status: PASS 
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
AURORA_RX_TOP/aurora_module_i/INIT_CLOCK_GEN_RX/inst/mmcm_adv_inst (MMCME2_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCME2_ADV_X0Y1
AURORA_RX_TOP/aurora_module_i/INIT_CLOCK_GEN_RX/inst/clkout1_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y4

Clock Rule: rule_gt_bufg
Status: PASS 
Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
AURORA_RX_TOP/aurora_module_i/aurora_8b10b_rx_i/inst/gt_wrapper_i/aurora_8b10b_rx_multi_gt_i/gt0_aurora_8b10b_rx_i/gtpe2_i (GTPE2_CHANNEL.TXOUTCLK) is provisionally placed by clockplacer on GTPE2_CHANNEL_X0Y2
and AURORA_RX_TOP/aurora_module_i/clock_module_i/user_clk_buf_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y5

 

I do have in mind what is shown in second attached diagram.

 

What i understand from this error is that clockplacer is not placing clocks in X0Y0 region. but why?

 

My full design is also attached 

Tags (1)
Untitled.jpg
Capture.PNG
0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
5,661 Views
Registered: ‎01-03-2008

Re: error: clockplacer not placing GTP clocks properly

This is a duplicate of another thread that you created with substantial discussion in it already.

http://forums.xilinx.com/t5/Implementation/GTP-set-LOC-property-warning/td-p/440010

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos