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Adventurer
Adventurer
5,363 Views
Registered: ‎07-08-2016

failing timing or implementation with ILA present

Hi Xilinx Community, 

 

This is a duplicate of my reply <here>, as I wanted to start my own thread, rather than replying to an already solved one. 

 

I have the same error as the OP in the above post (failing to meet timing when ILA present), however the steps suggested did not work for me. When I change the input clock frequency of the debug core to 125 MHz (I am clocking with ps7 FCLK1) the design still fails to meet timing. When I also check C_ENABLE_CLK_DIVIDER, the design fails implementation with the following failure messages: 

 

In place_design:

CRITICAL WARNING: [DRC 23-20] Rule violation (AVAL-46) v7v8_mmcm_fvco_rule1 - The current computed target frequency, FVCO, is out of range for cell dbg_hub/inst/USE_DIVIDER.U_GT_MMCM. The computed FVCO is 1600.000 MHz. The valid FVCO range for speed grade -1 is 600MHz to 1200MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 8.000, CLKIN1_PERIOD = 5.00000, and DIVCLK_DIVIDE = 1 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)).
This violation may be corrected by:
  1. The timer uses timing constraints for clock period or clock frequency that affect CLKIN1 to set cell attribute CLKIN1_PERIOD, over-riding any previous value. This may already be in place and, if so this violation will be resolved once Timing is run.  Otherwise, consider modifying timing constraints to adjust the CLKIN1_PERIOD and bring FVCO into the allowed range.
  2. In the absence of timing constraints that affect CLKIN1, consider modifying the cell CLKIN1_PERIOD to bring FVCO into the allowed range.
  3. If CLKIN1_PERIOD is satisfactory, modify the CLKFBOUT_MULT_F or DIVCLK_DIVIDE cell attributes to bring FVCO into the allowed range.

In route_design: 

[DRC 23-20] Rule violation (PDRC-34) MMCM_adv_ClkFrequency_div_no_dclk - The computed value 1600.000 MHz (CLKIN1_PERIOD, net FCLK_CLK1) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X1Y1 (cell dbg_hub/inst/USE_DIVIDER.U_GT_MMCM) falls outside the operating range of the MMCM VCO frequency for this device (600.00002122251317 - 1200.0000424450263 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (5.000000), multiplication factor CLKFBOUT_MULT_F (8.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

I am trying to follow the route_design error message's suggestion of changing the division factor in the MMCM, but I cannot figure out how to do it, as it is not present in the synthesized design. How might I do this? 

 

Also, I tried to follow the suggestion about relocating the debug hub to a separate clock region, but I can't figure out how to do this. Should I be generating a new clock in the fabric using a built-in PLL, or can one do this in a constraints file or using the floorplanning tools?

 

Any help or a nudge in the right direction would be GREATLY appreciated!

 

Thanks,

 

- Brett

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6 Replies
Moderator
Moderator
5,348 Views
Registered: ‎07-01-2015

Re: failing timing or implementation with ILA present

Hi @bigbrett,

 

There are 2 things here:

  1. VCO frequency
  2. Output frequency

Try to keep VCO frequency by setting the M and D value in the given range.

To achieve a require frequency, try changing "O" value.

Thanks,
Arpan
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Adventurer
Adventurer
5,340 Views
Registered: ‎07-08-2016

Re: failing timing or implementation with ILA present

@arpansur thanks for the response, I appreciate it

 

I think you might have misunderstood my issue....the problem is that I don't know where I should make those changes, as I don't know how to get to the MMCM inside the debug hub. None of the reference manuals (ug908 or ug949) seem to provide a solution.

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Xilinx Employee
Xilinx Employee
5,308 Views
Registered: ‎05-07-2015

Re: failing timing or implementation with ILA present

HI @bigbrett

after synthesis, you locate this MMCM in the netlist. and you can edit the MMCM properties in properties window below .
Edit M(CLKFBOUT_MULT_F), D(DIVCLK_DIVIDE)  and O(CLKOUT_DIVIDE) so that CLKIN*M/D value is within the 600 Mhz to 1000 Mhz range.

Thanks
Bharath
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Adventurer
Adventurer
5,279 Views
Registered: ‎07-08-2016

Re: failing timing or implementation with ILA present

@nagabhar it seems the only MMCM in my synthesized netlist is one that already was present before adding the debug hub.....it is an MMCM inside a gmii/rgmii converter IP. 

 

I am under the impression that when I check the clock divider enable box in the debug core properties, the tools should instantiate a NEW MMCM in the design....is this not correct? Or do I need to now manually configure another output on the existing MMCM to supply me with a clock output in the correct frequency? 

 

Apologies for the slew of questions, I really appreciate the help. I am just trying to make sure I am using the tools the way they are intended, and not developing bad habbits. 

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Visitor vpsampathvp
Visitor
1,746 Views
Registered: ‎09-03-2017

error dlatch

 concurrent assignment to a non-net q is not permitted

 

 

program:

 


module latch(rst,enable,data,q);
input rst,enable,data;
output q;
reg q;
always@(rst or data )
if(~rst)begin
q=1'b0;
end
else begin
q=data;
end
assign q=enable? 1'bz:data;
endmodule

 

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Moderator
Moderator
1,733 Views
Registered: ‎09-15-2016

Re: error dlatch

Hi @vpsampathvp,

 

You are trying to assign variable q with concurrent assignment hence the warning. They cannot be driven continuously here. You need net data type for assign.

 

Regards,
Prathik
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