12-08-2017 04:37 AM
I'd like to fix route from pin through a LUT and then to a reg, in the device window I chose the net and fix routing the nets.
But when I generate bit file there is error.
12-10-2017 03:08 AM
Are you seeing any error without using FIXED_ROUTE property? Check the following Answer Record to debug the issue:
12-10-2017 07:27 PM
@syedz, when I chose the net in device window and fix routing the net, there is an error.
"Error: [Vivado 12-1406] Cannot mark the 'site' location of instances fixed, Could not find a valid bel"
I have read the "https://www.xilinx.com/support/answers/54795.html", but it seems can't resolve my problem.
I first unroute and then route the net, and then I check the DRC, the error still exist.
12-10-2017 10:13 PM - edited 12-10-2017 10:14 PM
Did you get the values using get_property ROUTE command on routed design?
Which version of vivado are you using? Can you share the _routed.dcp file?
12-11-2017 12:14 AM - edited 12-11-2017 12:22 AM
@vemulad, I use get_property ROUTE, the result is a little different, I don't know why.
The first line is my constraint, the second line is the result of get_property ROUTE [get_nets ...]
I have revised all my constrs the same as the result of get_property ROUTE [get_nets ...], and there is not any change for the error.
What's more, I've add "dont_touch" in the verilog code for the wires and XOR, and it seems no difference.
I use vivado 2015.2 version.
Thank you very much!
12-11-2017 01:22 AM
Not sure how you have applied the property as when I route the design after unset IS_ROUTE_FIXED property and later reapplied IS_ROUTE_FIXED all the nets are successfully routed. I used Vivado 2017.1.
I was also able to generate the bitstream.
12-11-2017 03:55 AM - edited 12-11-2017 11:01 PM