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Registered: ‎10-28-2018

force_replication_on_nets question

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In implementation runme.log , vivado suggest use the  -force_replication_on_nets option to solve the timing issue.

But why do vivado do the -force_replication_on_nets by itself?

Or can vivado can write out all net to need to be replicated?

INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.827 | TNS=-2287.076 |
INFO: [Physopt 32-572] Net u_coreb033/u_cputop/u_Bisted_cpuram/RF256X8_u2/SRAM_i0/laddr[0] was not replicated.
Resolution: phys_opt_design can be forced to replicate a net driver using the option -force_replication_on_nets <list of net objects>.

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Registered: ‎01-22-2015

@khyu 

Or can vivado can write out all net to need to be replicated?
You can use the Tcl command, report_high_fanout_nets.

But why do vivado do the -force_replication_on_nets by itself?
When I first learned about this Vivado implementation option, I also thought it should be done always and automatically.  However, this approach leads to problems when your design is nearly filling the FPGA.

That is, for designs that nearly fill the FPGA, a more targeted approach is needed. Otherwise, replication may require more resources(registers) than available.  So, for example, you can use -force_replication_on_nets on specific nets (and not on all high fanout nets) as shown in the <this> post.

Other targeted approaches are from UG1231 opt_design -merge_equivalent_drivers -hier_fanout_limit and from UG904 -fanout_opt.

Note that fanout problems are best solved during Vivado implementation rather than during synthesis (eg. using MAX_FANOUT) as described on page 70 of UG904(v2019.2).

Cheers,
Mark

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Registered: ‎01-22-2015

@khyu 

Or can vivado can write out all net to need to be replicated?
You can use the Tcl command, report_high_fanout_nets.

But why do vivado do the -force_replication_on_nets by itself?
When I first learned about this Vivado implementation option, I also thought it should be done always and automatically.  However, this approach leads to problems when your design is nearly filling the FPGA.

That is, for designs that nearly fill the FPGA, a more targeted approach is needed. Otherwise, replication may require more resources(registers) than available.  So, for example, you can use -force_replication_on_nets on specific nets (and not on all high fanout nets) as shown in the <this> post.

Other targeted approaches are from UG1231 opt_design -merge_equivalent_drivers -hier_fanout_limit and from UG904 -fanout_opt.

Note that fanout problems are best solved during Vivado implementation rather than during synthesis (eg. using MAX_FANOUT) as described on page 70 of UG904(v2019.2).

Cheers,
Mark

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