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3,047 Views
Registered: ‎08-24-2012

hard macro PlanAhead

Hello,

 

I try to create a design which contains a hard macro component which is placed manually on a Slice from .ucf file. I used the PlanAhead flow for synthesis, implementation and bitstream. I added the -sd option to the ngdbuild tool and I didn't receive error regarding the hard macro.

But it returns me some warnings:

  • [EDIF 96] Could not resolve non-primitive black box cell 'FFT' defined in file 'main.edf' instantiated as 'FFT_inst'.
  • [Constraints 5] Cannot loc instance 'FFT_inst' at site SLICE_X1Y1, FFT_inst is not a leaf level instance ["D:\Xilinx141\PlanAhead\FirstPA\project_4\project_4.runs\impl_1_4\.constrs\top.ucf

 I opened the .ncd file with the FPGA Editor and the hard macro component was placed on a Slice, but not on the desired slice, specified in the .ucf file. The problem is that I need to manually placed the hard macro.

I also tried to run step by step the implementation phase: ngdbuild, map, par and it works: the hard macro was place on the desired Slice. Is there a problem with planhead and hard macro?

It is a posibility to run the implementation from PlanAhead and to obtain a hard macro placed wherever I want?

 

I use Xilinx 14.1

 

Thank you,

Alexandra Stanciu

 

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1 Reply
Xilinx Employee
Xilinx Employee
3,034 Views
Registered: ‎07-01-2008

Re: hard macro PlanAhead

Since you have an NCD file with the macro in it, check the name of the macro in FPGA Editor to see if your UCF constraint is correct.

 

Why are you creating a hard macro in the first place? There is very little that a hard macro can do that an RPM macro cannot and there are many pitfalls to their usage. I say this as perhaps the biggest advocate within Xilinx for maintaining hard macro support in ISE. It's good for creating configurations that Map cannot support but shoud otherwise be avoided. Please describe the problem you are trying to solve. There is likely a better way.

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