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Visitor srimipee
Visitor
2,307 Views
Registered: ‎05-28-2010

help needed in solving the timing errors on ml501 virtex-5 kit

hi

i'm doing my hw-cosimulation on ml501  kit,

i got few timing errors during PAR(placing n routing)

 

can anybody pls  help me in solving these errors.

 

 

the error i got is as followed

Number of Timing Constraints that were not applied: 1

 

Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.

 

----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing  

                                            |             |    Slack   | Achievable | Errors |    Score  

----------------------------------------------------------------------------------------------------------

* NET "bufgp_comp/IBUFG" PERIOD = 10 ns HIG | SETUP       |    -0.085ns|    10.085ns|       2|          93

  H 50%                                     | HOLD        |     0.158ns|            |       0|           0

------------------------------------------------------------------------------------------------------

  TS_clk_b681c1b5 = PERIOD TIMEGRP "clk_b68 | MINPERIOD   |     8.182ns|     1.818ns|       0|           0

  1c1b5" 10 ns HIGH 50%                     |             |            |            |        |           

------------------------------------------------------------------------------------------------------

  TS_J_TO_U = MAXDELAY FROM TIMEGRP "J_CLK" | SETUP       |    12.311ns|     2.689ns|       0|           0

   TO TIMEGRP "U_CLK" 15 ns                 | HOLD        |     0.357ns|            |       0|           0

------------------------------------------------------------------------------------------------------

  NET "jtag_iface/drck" PERIOD = 30 ns HIGH | SETUP       |    26.590ns|     3.410ns|       0|           0

   50%                                      | HOLD        |     0.361ns|            |       0|           0

------------------------------------------------------------------------------------------------------

 

 

1 constraint not met.

 

 

i'm also attaching a result file.

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1 Reply
Xilinx Employee
Xilinx Employee
2,299 Views
Registered: ‎09-28-2007

Re: help needed in solving the timing errors on ml501 virtex-5 kit

You can follow this post to lower the hardware co-sim clock frequency to 50 MHz:

http://forums.xilinx.com/t5/DSP-Tools/JTAG-co-simulation-model-generation-problem/m-p/33616#M1457

 

If you want to see the where the timing violations come from, load the post-PAR NCD file (<netlist>/xflow/jtagcosim_top.ncd) into Timing Analyzer and analyze for failed paths. 

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