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Contributor
Contributor
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Registered: ‎11-18-2017

hold time and set-up time in a FPGA

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Hello.

I'm using Vivado and my target device is ultrascale kintex.

In my design, there are lots of FFs.

I wonder if the hold, set-up times of primitives are predefined

or else I have to configure them with timing constraints(ex. the hold time of this FF is 10 ps).

Additionally, I wonder if the path delays are predefined 

or else I have to configure them with timing constraints(ex. the path( or propagation or maybe cell) delay from here to there is about 10 ps).

Thanks for your help.

 

ps. when I run the implementation, warning "[Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis" appears.

Do I have to write the timing constraints in my XDC like that I mentioned above?

I don't know what timing constraints I have to write in my XDC to do the timing analysis.

1 Solution

Accepted Solutions
229 Views
Registered: ‎01-22-2015

Re: hold time and set-up time in a FPGA

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@kimjaewon

     In my design, there are lots of FFs.  I wonder if the hold, set-up times of primitives are predefined
Vivado knows the setup and hold times for all the FFs inside your Kintex UltraScale FPGA.  You do not need to write timing constraints for this.  If you are interested in seeing typical values for FF setup and hold then look in Data Sheet, DS892.

     Additionally, I wonder if the path delays are predefined.
After you run implementation, Vivado will automatically know all the path delays in your design. You do not need to write timing constraints for this. 

When you use the FPGA to communicate with a FF that is external to the FPGA, you will then need to write timing constraints that specify both setup/hold of the external FF and path lengths to the external FF.

     [Timing 38-313] There are no user specified timing constraints....
     Do I have to write the timing constraints in my XDC like that I mentioned above?
This warning indicates that Vivado cannot find information about the clocks used in your design.  Normally, we use a Clock Management Tile (eg. MMCM) to create the clocks for our designs (see UG572, chapter 3 ).  You should use the Vivado IP called the Clocking Wizard (see PG065) to setup a Clock Management Tile for your project. When you use the Clocking Wizard IP, constraints that describe the created clocks will be automatically written for you. 

You can learn more about writing constraints for your Vivado project from:

Cheers,
Mark

1 Reply
230 Views
Registered: ‎01-22-2015

Re: hold time and set-up time in a FPGA

Jump to solution

@kimjaewon

     In my design, there are lots of FFs.  I wonder if the hold, set-up times of primitives are predefined
Vivado knows the setup and hold times for all the FFs inside your Kintex UltraScale FPGA.  You do not need to write timing constraints for this.  If you are interested in seeing typical values for FF setup and hold then look in Data Sheet, DS892.

     Additionally, I wonder if the path delays are predefined.
After you run implementation, Vivado will automatically know all the path delays in your design. You do not need to write timing constraints for this. 

When you use the FPGA to communicate with a FF that is external to the FPGA, you will then need to write timing constraints that specify both setup/hold of the external FF and path lengths to the external FF.

     [Timing 38-313] There are no user specified timing constraints....
     Do I have to write the timing constraints in my XDC like that I mentioned above?
This warning indicates that Vivado cannot find information about the clocks used in your design.  Normally, we use a Clock Management Tile (eg. MMCM) to create the clocks for our designs (see UG572, chapter 3 ).  You should use the Vivado IP called the Clocking Wizard (see PG065) to setup a Clock Management Tile for your project. When you use the Clocking Wizard IP, constraints that describe the created clocks will be automatically written for you. 

You can learn more about writing constraints for your Vivado project from:

Cheers,
Mark