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Visitor pjzjj
Visitor
345 Views
Registered: ‎12-29-2018

hold violation fix

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 Now, I am doing one project for emulation. And the lut utilization  of the design is 70% for virtex ultrascale 440 FPGA. 

I have two question:

1. when tools excutes second round for place command during implemention, the tool happend the following ERROR. How to solve the ERROR without reducing  the design utilization?

WARNING: [Place 30-34] Design utilization is very high. Please run report_utilization command to see design utilization.
ERROR: [Place 30-4] Design utilization is very high. Run report_utilization command to see design utilization.
Abandoning placement as chances are very low that placement is possible.

2. according to the first round implemention,  the hold violation of the following timing path  is up -0.416ns. the timing path is in the following txt

How to reduce the violation?

 

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1 Solution

Accepted Solutions
Scholar drjohnsmith
Scholar
318 Views
Registered: ‎07-09-2009

Re: hold violation fix

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Unless your desing is really very full,

   in which case you need to look closely at the algorithums your using in the fpga,

One cause of this sort of problem, is multiple clocking,

Vivado by default assumes all clocks are related, and it has to find a timming fit.

     Check you have marked cross clocks as not needing to be timed as yo have taken care of the clock crossing in the clode.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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5 Replies
Xilinx Employee
Xilinx Employee
326 Views
Registered: ‎05-22-2018

Re: hold violation fix

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Hi @pjzjj ,

Regarding bypassing the error please check the below post, might be helpful:

https://forums.xilinx.com/t5/Implementation/Place-30-4-Error/td-p/658011 

Thanks,

Raj

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Scholar drjohnsmith
Scholar
319 Views
Registered: ‎07-09-2009

Re: hold violation fix

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Unless your desing is really very full,

   in which case you need to look closely at the algorithums your using in the fpga,

One cause of this sort of problem, is multiple clocking,

Vivado by default assumes all clocks are related, and it has to find a timming fit.

     Check you have marked cross clocks as not needing to be timed as yo have taken care of the clock crossing in the clode.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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Visitor pjzjj
Visitor
269 Views
Registered: ‎12-29-2018

Re: hold violation fix

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Thank you for your quick reply. I will try the soultion.

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Xilinx Employee
Xilinx Employee
192 Views
Registered: ‎05-22-2018

Re: hold violation fix

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Hi @pjzjj ,

Were you able to try out the solution?

Did you issue got resolved?

Please update.

Thanks,

Raj

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Visitor pjzjj
Visitor
178 Views
Registered: ‎12-29-2018

Re: hold violation fix

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Thank you for suggesttion.

After setting the paramter, the next round for implementition really continue to run. but, the timing violation of the second implementition is more bad.

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