cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Participant
Participant
411 Views
Registered: ‎04-03-2017

how do I disconnect an output from any package_pins?

I've got one design that I want to put onto two different zynq boards.

The only differences are the physical pin placements.  I have the design process automated, so I would like to be able to just switch out a xdc constraint file to rebuild the design for a different board.

Unfortunately, one design needs a few more outputs than the other.  I tried to leave those outputs unconstrained, but Vivado just assigns them to random pins and reports rule violations NSTD-1 and UCIO-1 that I have not constrained the IOSTANDARD or LOC, respectively.

In order to disconnect pins, do I have to manually maintain the wrapper vhd file around the block diagram, or is there some constraint that I can set that disconnects my outputs from any package pins?

I saw a similar question here: https://forums.xilinx.com/t5/Implementation/Leave-top-level-ports-unplaced/td-p/670336 but couldn't get that constraint to do anything. I'm using Vivado 2016.2.  I posted a similar question here https://forums.xilinx.com/t5/Vivado-TCL-Community/xdc-package-pin-make-no-connection/m-p/1057530#M8666 , but markg's proposed solution didn't work.

0 Kudos
Reply
1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
383 Views
Registered: ‎05-22-2018

Hi @trehcir ,

If this is top level port and it is unconnected then the tool cannot trim it. During Implementation even if you dont assign LOC constraint the tool chooses some package pin for the top level port. If you want you can downgrade the DRC or modify the RTL to remove these unused top level ports.

This AR can be helpful http://www.xilinx.com/support/answers/56354.html 

Thanks,

Raj

0 Kudos
Reply