11-25-2020 09:41 AM
I am getting a failure during placement and I'm wondering how I should go about debugging it. Before you ask, no I cannot provide a dcp of the design. Placer log is as follows:
Command: place_design -directive Default
Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev'
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'Default' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 8616 ; free virtual = 37475
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1036153ba
Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.23 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 8615 ; free virtual = 37475
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 8552 ; free virtual = 37412
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 163529480
Time (s): cpu = 00:01:25 ; elapsed = 00:00:53 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 8564 ; free virtual = 37423
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 254af2af6
Time (s): cpu = 00:04:16 ; elapsed = 00:02:01 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 7766 ; free virtual = 36625
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 254af2af6
Time (s): cpu = 00:04:18 ; elapsed = 00:02:02 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 7766 ; free virtual = 36625
Phase 1 Placer Initialization | Checksum: 254af2af6
Time (s): cpu = 00:04:20 ; elapsed = 00:02:04 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 7762 ; free virtual = 36621
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 181cd049d
Time (s): cpu = 00:12:23 ; elapsed = 00:05:19 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 7352 ; free virtual = 36212
Phase 2.2 Physical Synthesis In Placer
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-64] No nets found for fanout-optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 8090 ; free virtual = 36941
Summary of Physical Synthesis Optimizations
============================================
----------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
----------------------------------------------------------------------------------------------------------------------------------------
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:02 |
| Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 0 | 0 | 0 | 6 | 00:00:03 |
----------------------------------------------------------------------------------------------------------------------------------------
Phase 2.2 Physical Synthesis In Placer | Checksum: 1fdc7852b
Time (s): cpu = 00:23:32 ; elapsed = 00:12:25 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 8084 ; free virtual = 36935
Phase 2 Global Placement | Checksum: 214f074d2
Time (s): cpu = 00:27:02 ; elapsed = 00:14:35 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 8059 ; free virtual = 36912
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 214f074d2
Time (s): cpu = 00:27:07 ; elapsed = 00:14:36 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 7984 ; free virtual = 36836
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1fc79dc54
Time (s): cpu = 00:28:43 ; elapsed = 00:15:01 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 7694 ; free virtual = 36546
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 225eac4ef
Time (s): cpu = 00:28:53 ; elapsed = 00:15:04 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 7671 ; free virtual = 36524
Phase 3.4 IO Cut Optimizer
Phase 3.4 IO Cut Optimizer | Checksum: 1f7f2c7aa
Time (s): cpu = 00:28:56 ; elapsed = 00:15:06 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 7671 ; free virtual = 36524
Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: 25741081c
Time (s): cpu = 00:30:24 ; elapsed = 00:15:29 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 7581 ; free virtual = 36434
Phase 3.6 Small Shape Clustering
Phase 3.6 Small Shape Clustering | Checksum: 1845199ff
Time (s): cpu = 00:31:46 ; elapsed = 00:16:40 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 7421 ; free virtual = 36274
Phase 3.7 Flow Legalize Slice Clusters
Phase 3.7 Flow Legalize Slice Clusters | Checksum: 1c9a19e5d
Time (s): cpu = 00:31:52 ; elapsed = 00:16:42 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 7453 ; free virtual = 36306
Phase 3.8 Slice Area Swap
Phase 3.8 Slice Area Swap | Checksum: 21c1fb235
Time (s): cpu = 00:33:25 ; elapsed = 00:17:53 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 7295 ; free virtual = 36149
Phase 3.9 Commit Slice Clusters
Phase 3.9 Commit Slice Clusters | Checksum: 1b29420a3
Time (s): cpu = 00:34:55 ; elapsed = 00:18:20 . Memory (MB): peak = 7801.152 ; gain = 0.000 ; free physical = 7207 ; free virtual = 36061
Phase 3.10 Place Remaining
Phase 3.10 Place Remaining | Checksum: 20001a519
Time (s): cpu = 00:35:01 ; elapsed = 00:18:23 . Memory (MB): peak = 7807.941 ; gain = 6.789 ; free physical = 7199 ; free virtual = 36053
Phase 3.11 Re-assign LUT pins
Phase 3.11 Re-assign LUT pins | Checksum: 20d627e6f
Time (s): cpu = 00:35:21 ; elapsed = 00:18:40 . Memory (MB): peak = 7807.945 ; gain = 6.793 ; free physical = 7260 ; free virtual = 36113
Phase 3.12 Pipeline Register Optimization
Phase 3.12 Pipeline Register Optimization | Checksum: 1c34a4d52
Time (s): cpu = 00:35:45 ; elapsed = 00:19:09 . Memory (MB): peak = 7807.945 ; gain = 6.793 ; free physical = 7364 ; free virtual = 36217
Phase 3.13 Fast Optimization
Phase 3.13 Fast Optimization | Checksum: f5080051
Time (s): cpu = 00:41:14 ; elapsed = 00:21:10 . Memory (MB): peak = 7909.289 ; gain = 108.137 ; free physical = 7090 ; free virtual = 35943
Phase 3 Detail Placement | Checksum: f5080051
Time (s): cpu = 00:41:15 ; elapsed = 00:21:12 . Memory (MB): peak = 7909.289 ; gain = 108.137 ; free physical = 7091 ; free virtual = 35945
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1326a8486
Phase 4.1.1.1 BUFG Insertion
<snip 20x Place 46-33 INFOs>
INFO: [Place 46-46] BUFG insertion identified 20 candidate nets, 0 success, 0 bufg driver replicated, 20 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason
Phase 4.1.1.1 BUFG Insertion | Checksum: 1326a8486
Time (s): cpu = 00:46:32 ; elapsed = 00:22:30 . Memory (MB): peak = 8118.961 ; gain = 317.809 ; free physical = 7200 ; free virtual = 36054
INFO: [Place 30-746] Post Placement Timing Summary WNS=-2.558. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 2161ee593
Time (s): cpu = 00:48:08 ; elapsed = 00:23:18 . Memory (MB): peak = 8118.961 ; gain = 317.809 ; free physical = 7158 ; free virtual = 36012
Phase 4.1 Post Commit Optimization | Checksum: 2161ee593
Time (s): cpu = 00:48:10 ; elapsed = 00:23:20 . Memory (MB): peak = 8118.961 ; gain = 317.809 ; free physical = 7158 ; free virtual = 36012
WARNING: [Place 46-14] The placer has determined that this design is highly congested and may have difficulty routing. Run report_design_analysis -congestion for a detailed report.
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 2161ee593
Time (s): cpu = 00:48:16 ; elapsed = 00:23:23 . Memory (MB): peak = 8118.961 ; gain = 317.809 ; free physical = 7173 ; free virtual = 36027
ERROR: [Place 30-433] Unplaced instances found. If the tcl command place_design -verbose is used, all unplaced instances will be shown below. Otherwise, only 1 example instance will be shown.
U_AXI_DMA/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_2
Resolution: For technical support on this issue, please visit http://www.xilinx.com/support
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2161ee593
Time (s): cpu = 00:48:17 ; elapsed = 00:23:24 . Memory (MB): peak = 8118.961 ; gain = 317.809 ; free physical = 7173 ; free virtual = 36027
ERROR: [Place 30-99] Placer failed with error: 'Found unplaced instances.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 19dbfeb14
Time (s): cpu = 00:48:22 ; elapsed = 00:23:29 . Memory (MB): peak = 8118.961 ; gain = 317.809 ; free physical = 7705 ; free virtual = 36559
INFO: [Common 17-83] Releasing license: Implementation
214 Infos, 3 Warnings, 2 Critical Warnings and 3 Errors encountered.
place_design failed
When I run the suggested report_design_analysis -congestion, I don't get anything in the report because apparently all the other placement information gets nuked after the placer fails? Not sure, but the gui report tells me the design has not been placed, thus no report.
How should I approach this?
11-25-2020 12:20 PM - edited 11-25-2020 12:22 PM
@zalfrin ,
Did you find any messages related to this........?
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Are there any? If so they must be fixed first.
If there isn't any, did you try PnR multiple times? If yes, is the outcome same every time?
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11-25-2020 05:45 PM
You can try to run place_design -verbose to check whether there is other instance unplaced.
Can you also try place_design in Vivado 2020.2?