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ssampath
Voyager
Voyager
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Registered: ‎10-12-2016

how to decide the io standards of the ports for the FPGA top ports ?

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Hi Friends,

Am confusing while assigning IO STANDARD's for the top module ports in the vivado.

1) many standards are there, how to decide what to choose ?

2) suppose i am using VCU118 board and  i have i/f ports like CAN,DDR,DP etc. what are the parameters i should consider ?

3) if i chosse wrong one, will it cause any issue functional as well as physical ?

Any help or suggestions are highly appreciated. 

-Sam

 

 

-Sampath
1 Solution

Accepted Solutions
1,477 Views
Registered: ‎01-22-2015

@ssampath 

-adding just a little to what others have said:

  1. KNOW YOUR BOARD:  when you are trying to decide the IOSTANDARD for a pin then you need to get the board schematic and find the FPGA bank type (eg. HR, HP, HD) and you need to find VCCO for the bank.

  2. VIVADO DOESN'T KNOW EVERTHING:  If you correctly specify the FPGA part number to Vivado then Vivado knows the bank type for each pin.  Vivado does not know what VCCO you are using to power the bank.  Vivado will guess the value of VCCO for a bank based on what IOSTANDARDs you assign to pins in the bank.  However, if you assign the wrong IOSTANDARDs then Vivado will guess the wrong value of VCCO.

  3. GO-TO TABLES: The SelectIO User Guide for your FPGA has tables that tell you what IOSTANDARDs you can use if you know bank-type and VCCO.  For 7-Series FPGAs, the go-to table is Table 1-55 in UG471.  For UltraScale FPGAs, the go-to tables are Tables 1-77 and 3-2 in UG571. 

  4. IMPORTANT?:  you betcha!  Selecting the wrong IOSTANDARD can damage the FPGA and/or devices connected to the FPGA.  However, even when you select the correct IOSTANDARD, you should still go to the FPGA datasheet to check compatibility of the IOSTANDARD with the external device.  For single-ended standards (eg. LVCMOS), check VIH, VIL, VOH, VOL.  For differential standards (eg. LVDS) check VICM, VIDIFF, VOCM, VODIFF.

Mark

 

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10 Replies
rshekhaw
Xilinx Employee
Xilinx Employee
1,554 Views
Registered: ‎05-22-2018

Hi @ssampath ,

You can automatically assign I/O ports to package pins in an open synthesized design. The Vivado IDE obeys I/O standard and differential pair rules and places global clock pins appropriately. Please check page no.46 of below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug899-vivado-io-clock-planning.pdf

Thanks,

Raj

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drjohnsmith
Teacher
Teacher
1,542 Views
Registered: ‎07-09-2009
Its a good , fundamental question.

The FPGA as you have seen, can support many different IO standards.
This is to accommodate the many different chips it can interface to.

So a camera interface might need a MIPI CIS voltage level / standard, whilst DDR 4 will need another.

So the IO standard of each FPGA pin is selected depending what its interfacing to.

And yes, if you drive out of an FPGA 3v3 into a device designed to expect 1v2, you will blow the device. If your FPGA is set to accept 1v2, and a device is driving it with 3v3, you will blow the FPGA .

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andrewlan
Explorer
Explorer
1,527 Views
Registered: ‎06-25-2014

Just to add that the VCU118 will provide a board schematic and example designs where they will contain IO constraints that you can look at to get some idea on IO standards vs interfaces/devices/FPGA Bank Voltages etc...

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1,507 Views
Registered: ‎07-23-2019

 

It depends on the chips you interface to. Basically, it is decided when you decided what to connect. for many low-speed protocols (CAN, SPI, Uart, etc) LVCMOS should be fine. Another thing to check is the bank voltage matches with the connected device. Also, for each IO pin you can select a pull-up/down and the drive strength, these are usually tunable at debug time.

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bruce_karaffa
Scholar
Scholar
1,503 Views
Registered: ‎06-21-2017

Another thing you need to consider is the VCCO of the bank that the IO pin is on.  If the bank has a VCCO of 1.8V, you cannot set an IO standard to LVCMOS25.  Likewise if the bank is powered by 3.3V, you cannot set the bank to LVCMOS18.  There are also rules about what voltages can be used to power banks where the interfacing signal is LVDS.  The schematic or users manual should tell you the VCCO of each bank.  These can be adjusted for some boards.  The Select IO Users Guide for the chip (7 series, Ultrascale, etc.) will tell you the rules for assigning IO standards,

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1,478 Views
Registered: ‎01-22-2015

@ssampath 

-adding just a little to what others have said:

  1. KNOW YOUR BOARD:  when you are trying to decide the IOSTANDARD for a pin then you need to get the board schematic and find the FPGA bank type (eg. HR, HP, HD) and you need to find VCCO for the bank.

  2. VIVADO DOESN'T KNOW EVERTHING:  If you correctly specify the FPGA part number to Vivado then Vivado knows the bank type for each pin.  Vivado does not know what VCCO you are using to power the bank.  Vivado will guess the value of VCCO for a bank based on what IOSTANDARDs you assign to pins in the bank.  However, if you assign the wrong IOSTANDARDs then Vivado will guess the wrong value of VCCO.

  3. GO-TO TABLES: The SelectIO User Guide for your FPGA has tables that tell you what IOSTANDARDs you can use if you know bank-type and VCCO.  For 7-Series FPGAs, the go-to table is Table 1-55 in UG471.  For UltraScale FPGAs, the go-to tables are Tables 1-77 and 3-2 in UG571. 

  4. IMPORTANT?:  you betcha!  Selecting the wrong IOSTANDARD can damage the FPGA and/or devices connected to the FPGA.  However, even when you select the correct IOSTANDARD, you should still go to the FPGA datasheet to check compatibility of the IOSTANDARD with the external device.  For single-ended standards (eg. LVCMOS), check VIH, VIL, VOH, VOL.  For differential standards (eg. LVDS) check VICM, VIDIFF, VOCM, VODIFF.

Mark

 

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ssampath
Voyager
Voyager
1,462 Views
Registered: ‎10-12-2016

HI All,

Thanks a lot, lots of doubts are cleared, but still having few.

My main concern is about differential signals io standards. main confusion at LVDS and HSTL?

what to choose when differential signals are comming into picture, LVDS or HSTL or any other differential standard ?

-Sampath

-Sampath
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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009
LVDS and HSTL are very different standards,

If you have a free hand to select both ends, I'd go for LVDS ,
if one end is pre defined, the other has to be the same.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Registered: ‎07-23-2019
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ssampath
Voyager
Voyager
1,352 Views
Registered: ‎10-12-2016

 

Thanks to all for spending valuable time and good suggestions. I got some idea to go ahead.

-Sam

-Sampath
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