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Participant
Participant
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Registered: ‎08-09-2020

how to fix a nearby slice around a pad?

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The net delay is too large. because the slice is far from  the pad.

1>how to get an  available slice  list  around a pad?

2>can i select a nearby slice for a pad random?

 

slice.png
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Registered: ‎01-22-2015

@ha4456 

As @archangel-lightworks says, Vivado timing analysis usually prevents net delay from being too large. 

However, maybe the path from your port/pad, MY_PORT1, to a register, MY_REG1, is not undergoing timing analysis?  You can force this path to undergo timing analysis using constraints similar to the following:

set_input_delay -clock MY_CLK1 X.XX [get_ports MY_PORT1]
set_max_delay -datapath_only -from [get_ports MY_PORT1] -to [get_cells MY_REG1_reg] Y.YY


The set_input_delay constraint creates a valid timing path that effectively extends from an imaginary register outside the FPGA and through MY_PORT1 to MY_REG1.  In this constraint, MY_CLK1 is any clock in your design and X.XX is a delay number (more on this later). 

The set_max_delay -datapath_only constraint limits the delay from the imaginary external register to MY_REG1 to be Y.YY ns. 

So, the method is to fiddle with values for X.XX and Y.YY until the path just passes timing analysis.  Then, MY_REG1 and things between MY_PORT1 and MY_REG1 should be placed in a slice that is near MY_PORT1.

Cheers,
Mark

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Registered: ‎07-23-2019

 

Vivado places functions where possible and it optimizes a number of parameters. Even if you were able to force a function into some slice, the result will probably be worse in other aspects.

The normal way of dealing with timing closure is by using timing constraints, not fiddling with slice locations.

Highlighted
581 Views
Registered: ‎01-22-2015

@ha4456 

As @archangel-lightworks says, Vivado timing analysis usually prevents net delay from being too large. 

However, maybe the path from your port/pad, MY_PORT1, to a register, MY_REG1, is not undergoing timing analysis?  You can force this path to undergo timing analysis using constraints similar to the following:

set_input_delay -clock MY_CLK1 X.XX [get_ports MY_PORT1]
set_max_delay -datapath_only -from [get_ports MY_PORT1] -to [get_cells MY_REG1_reg] Y.YY


The set_input_delay constraint creates a valid timing path that effectively extends from an imaginary register outside the FPGA and through MY_PORT1 to MY_REG1.  In this constraint, MY_CLK1 is any clock in your design and X.XX is a delay number (more on this later). 

The set_max_delay -datapath_only constraint limits the delay from the imaginary external register to MY_REG1 to be Y.YY ns. 

So, the method is to fiddle with values for X.XX and Y.YY until the path just passes timing analysis.  Then, MY_REG1 and things between MY_PORT1 and MY_REG1 should be placed in a slice that is near MY_PORT1.

Cheers,
Mark

View solution in original post

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Participant
Participant
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Registered: ‎08-09-2020

@ 

HI, can you guide me to fix the constrain? 

thanks in advance.

1310a.png
1310b.png
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Teacher
Teacher
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Registered: ‎07-09-2009
Can you share your current constraints file,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Participant
Participant
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Registered: ‎08-09-2020

The xdc file can't be attached. i just paste them.thanks!

create_clock -name {sysclk1_300_p} [get_ports {sysclk1_300_p}] -period {3.3333}
create_clock -name {emmc_clk_out} [get_ports emmc_clkout] -period 40
create_clock -name {sysclk2_300_p} [get_ports {sysclk2_300_p}] -period {3.3333}
create_clock -name {phy0_rx_clk} [get_ports phy0_rx_clk] -period 8
create_generated_clock -name phy0_tx_clk -divide_by 1 -source [get_ports phy0_rx_clk] [get_ports phy0_tx_clk]
create_clock -name {ulpi_clk} [get_ports {ulpi_clk}] -period {16.667}
create_clock -name {usb3pipe_clk250} [get_ports ti_pipe3_250MHz] -period 4
create_generated_clock -name usb3tx_clk250 -source [get_ports ti_pipe3_250MHz] -divide_by 1 [get_pins usb3_drd/usb3_pll/inst/clkout1_buf/O]


set_property PACKAGE_PIN BD28 [get_ports "sysclk1_300_p"]
set_property IOSTANDARD LVDS [get_ports "sysclk1_300_p"]
set_property PACKAGE_PIN BE28 [get_ports "sysclk1_300_n"]
set_property IOSTANDARD LVDS [get_ports "sysclk1_300_n"]
set_property DIFF_TERM true [get_ports sysclk1_300_p]
set_property DIFF_TERM true [get_ports sysclk1_300_n]

set_property PACKAGE_PIN AY45 [get_ports "led0"]
set_property IOSTANDARD LVCMOS18 [get_ports "led0"]
set_property PACKAGE_PIN BB47 [get_ports "led1"]
set_property PACKAGE_PIN BA44 [get_ports "led2"]
set_property PACKAGE_PIN AV48 [get_ports "led3"]
set_property PACKAGE_PIN AV47 [get_ports "led4"]
set_property IOSTANDARD LVCMOS18 [get_ports "led1"]
set_property IOSTANDARD LVCMOS18 [get_ports "led2"]
set_property IOSTANDARD LVCMOS18 [get_ports "led3"]
set_property IOSTANDARD LVCMOS18 [get_ports "led4"]

set_property PACKAGE_PIN BC29 [get_ports "sysclk2_300_p"]
set_property IOSTANDARD LVDS [get_ports "sysclk2_300_p"]
set_property PACKAGE_PIN BD29 [get_ports "sysclk2_300_n"]
set_property IOSTANDARD LVDS [get_ports "sysclk2_300_n"]


set_property PACKAGE_PIN BN33 [get_ports "rst_n"]
set_property IOSTANDARD LVCMOS18 [get_ports "rst_n"]
set_property IOSTANDARD LVCMOS18 [get_ports "f1_rst"]
set_property IOSTANDARD LVCMOS18 [get_ports "f1_clk"]


set_clock_groups -name async_group0 -asynchronous -group [get_clocks c0_sys_clk_p -include_generated_clocks] \
-group [get_clocks ulpi_clk] \
-group [get_clocks usb3pipe_clk250 -include_generated_clocks] \
-group [get_clocks {phy0_rx_clk phy0_tx_clk} ] \
-group [get_clocks {emmc_clk_out emmc_clk_drv}] \
-group [get_clocks c1_sys_clk_p -include_generated_clocks] \
-group [get_clocks sysclk2_300_p -include_generated_clocks] \
-group [get_clocks sysclk1_300_p -include_generated_clocks]

 


set_property IOSTANDARD LVCMOS18 [get_ports "f1_*"]

 

 

set_property PACKAGE_PIN BA39 [get_ports "f1_por"]

set_property PACKAGE_PIN BA32 [get_ports "f1_rst"]
set_property PACKAGE_PIN BB31 [get_ports "f1_clk"]


set_property PACKAGE_PIN BL37 [get_ports "uart0_rxd"]
set_property PACKAGE_PIN BP33 [get_ports "uart0_txd"]
set_property IOSTANDARD LVCMOS18 [get_ports "uart0_*"]

set_input_delay -clock [get_clocks clk_out3_clk_wiz_0] -min 0 [get_ports uart0_rxd]
set_input_delay -clock [get_clocks clk_out3_clk_wiz_0] -max 28 [get_ports uart0_rxd]
set_output_delay -clock [get_clocks clk_out3_clk_wiz_0] -min 0 [get_ports uart0_txd]
set_output_delay -clock [get_clocks clk_out3_clk_wiz_0] -max 24 [get_ports uart0_txd]
set_false_path -from [get_clocks clk_out2_clk_wiz_0] -to [get_clocks clk_out3_clk_wiz_0]
set_false_path -from [get_clocks clk_out3_clk_wiz_0] -to [get_clocks clk_out2_clk_wiz_0]
set_property IOSTANDARD LVCMOS18 [get_ports "i2c_*"]

 

set ulpi_input {ulpi_data[*] ulpi_dir ulpi_nxt}
set ulpi_output {ulpi_data[*] ulpi_stp}
set_input_delay -clock [get_clocks ulpi_clk] -max 8 [get_ports $ulpi_input]
set_output_delay -clock [get_clocks ulpi_clk] -max 5.7 [get_ports $ulpi_output]
set_false_path -from [get_ports ulpi_data[*]] -to [get_ports ulpi_stp]

set_property PACKAGE_PIN AU24 [get_ports " usb3h_TxData[0] " ]
set_property PACKAGE_PIN AV24 [get_ports " usb3h_TxData[1] " ]
set_property PACKAGE_PIN AY23 [get_ports " usb3h_TxData[2] " ]
set_property PACKAGE_PIN BA23 [get_ports " usb3h_TxData[3] " ]
set_property PACKAGE_PIN BC24 [get_ports " usb3h_TxData[4] " ]
set_property PACKAGE_PIN BD24 [get_ports " usb3h_TxData[5] " ]
set_property PACKAGE_PIN AU16 [get_ports " usb3h_TxData[6] " ]
set_property PACKAGE_PIN AV16 [get_ports " usb3h_TxData[7] " ]
set_property PACKAGE_PIN AT17 [get_ports " usb3h_TxData[8] " ]
set_property PACKAGE_PIN AU17 [get_ports " usb3h_TxData[9] " ]
set_property PACKAGE_PIN AT23 [get_ports " usb3h_TxData[10] " ]
set_property PACKAGE_PIN AT22 [get_ports " usb3h_TxData[11] " ]
set_property PACKAGE_PIN AT12 [get_ports " usb3h_TxData[12] " ]
set_property PACKAGE_PIN AU12 [get_ports " usb3h_TxData[13] " ]
set_property PACKAGE_PIN AV13 [get_ports " usb3h_TxData[14] " ]
set_property PACKAGE_PIN AW13 [get_ports " usb3h_TxData[15] " ]
set_property PACKAGE_PIN AY18 [get_ports " usb3h_TxDataK[0] " ]
set_property PACKAGE_PIN BA18 [get_ports " usb3h_TxDataK[1] " ]
set_property PACKAGE_PIN BD20 [get_ports " ulpi_clk " ]
set_property PACKAGE_PIN BD16 [get_ports " ulpi_data[0] " ]
set_property PACKAGE_PIN BE16 [get_ports " ulpi_data[1] " ]
set_property PACKAGE_PIN BK17 [get_ports " ulpi_data[2] " ]
set_property PACKAGE_PIN BK16 [get_ports " ulpi_data[3] " ]
set_property PACKAGE_PIN BG19 [get_ports " ulpi_data[4] " ]
set_property PACKAGE_PIN BH19 [get_ports " ulpi_data[5] " ]
set_property PACKAGE_PIN BG22 [get_ports " ulpi_data[6] " ]
set_property PACKAGE_PIN BH22 [get_ports " ulpi_data[7] " ]
set_property PACKAGE_PIN BF25 [get_ports " ulpi_dir " ]
set_property PACKAGE_PIN BD14 [get_ports " ulpi_stp " ]
set_property PACKAGE_PIN BG25 [get_ports " ulpi_nxt " ]
set_property PACKAGE_PIN AU19 [get_ports " usb3h_TxDetectRxLoopbk " ]
set_property PACKAGE_PIN BD13 [get_ports " usb3h_TxMargin[0] " ]
set_property PACKAGE_PIN BN18 [get_ports " usb3h_TxMargin[1] " ]
set_property PACKAGE_PIN BP18 [get_ports " usb3h_TxMargin[2] " ]
set_property PACKAGE_PIN BB20 [get_ports " usb3h_PowerPresent " ]
set_property PACKAGE_PIN BK15 [get_ports " usb3h_TxOnesZeros " ]
set_property PACKAGE_PIN AT25 [get_ports " usb3h_vbus_en " ]
set_property PACKAGE_PIN AU25 [get_ports " ti1310por " ]
set_property PACKAGE_PIN AU22 [get_ports " usb3h_RxData[0] " ]
set_property PACKAGE_PIN AV22 [get_ports " usb3h_RxData[1] " ]
set_property PACKAGE_PIN BF24 [get_ports " usb3h_RxData[2] " ]
set_property PACKAGE_PIN BF23 [get_ports " usb3h_RxData[3] " ]
set_property PACKAGE_PIN BJ20 [get_ports " usb3h_RxData[4] " ]
set_property PACKAGE_PIN BJ19 [get_ports " usb3h_RxData[5] " ]
set_property PACKAGE_PIN BM17 [get_ports " usb3h_RxData[6] " ]
set_property PACKAGE_PIN BN17 [get_ports " usb3h_RxData[7] " ]
set_property PACKAGE_PIN AY25 [get_ports " usb3h_RxData[8] " ]
set_property PACKAGE_PIN BA25 [get_ports " usb3h_RxData[9] " ]
set_property PACKAGE_PIN AT14 [get_ports " usb3h_RxData[10] " ]
set_property PACKAGE_PIN AU14 [get_ports " usb3h_RxData[11] " ]
set_property PACKAGE_PIN BE17 [get_ports " usb3h_RxData[12] " ]
set_property PACKAGE_PIN BF17 [get_ports " usb3h_RxData[13] " ]
set_property PACKAGE_PIN BH11 [get_ports " usb3h_RxData[14] " ]
set_property PACKAGE_PIN BJ11 [get_ports " usb3h_RxData[15] " ]
set_property PACKAGE_PIN BA15 [get_ports " usb3h_RxDataK[0] " ]
set_property PACKAGE_PIN BB15 [get_ports " usb3h_RxDataK[1] " ]
set_property PACKAGE_PIN BA19 [get_ports " ti_pipe3_250MHz " ]
set_property PACKAGE_PIN BC14 [get_ports " usb3h_RxValid " ]
set_property PACKAGE_PIN BC23 [get_ports " TX_CLK " ]
set_property PACKAGE_PIN AY20 [get_ports " usb3h_PhyStatus " ]
set_property PACKAGE_PIN AW20 [get_ports " usb3h_RxElecIdle " ]
set_property PACKAGE_PIN BB24 [get_ports " usb3h_RxPolarity " ]
set_property PACKAGE_PIN AY17 [get_ports " usb3h_PowerDown[0] " ]
set_property PACKAGE_PIN BA17 [get_ports " usb3h_PowerDown[1] " ]
set_property PACKAGE_PIN BP21 [get_ports " usb3h_RxStatus[0] " ]
set_property PACKAGE_PIN BP20 [get_ports " usb3h_RxStatus[1] " ]
set_property PACKAGE_PIN BA20 [get_ports " usb3h_RxStatus[2] " ]
set_property PACKAGE_PIN BN19 [get_ports " usb3h_TxDeemph[0] " ]
set_property PACKAGE_PIN BP19 [get_ports " usb3h_TxDeemph[1] " ]
set_property PACKAGE_PIN AT19 [get_ports " usb3h_reset_n " ]
set_property PACKAGE_PIN BG14 [get_ports " usb3h_RxTermination " ]
set_property PACKAGE_PIN BH14 [get_ports " usb3h_Rate " ]
set_property PACKAGE_PIN BC13 [get_ports " usb3h_TxElecIdle " ]
set_property PACKAGE_PIN BL15 [get_ports " usb3h_ElasBufferMode " ]
set_property PACKAGE_PIN BA24 [get_ports " usb3h_TxSwing " ]
set_property IOSTANDARD LVCMOS18 [get_ports "usb3h_* "]
set_property IOSTANDARD LVCMOS18 [get_ports "TX_CLK "]
set_property IOSTANDARD LVCMOS18 [get_ports "ti_pipe3_250MHz "]
set_property IOSTANDARD LVCMOS18 [get_ports "ti1310por "]
set_property IOSTANDARD LVCMOS18 [get_ports "ulpi_*"]
set_input_delay -clock [get_clocks usb3pipe_clk250] -min 0 [get_ports usb3h_RxData[*]]
set_input_delay -clock [get_clocks usb3pipe_clk250] -max 2 [get_ports usb3h_RxData[*]]
set_input_delay -clock [get_clocks usb3pipe_clk250] -min 0 [get_ports usb3h_RxDataK[*]]
set_input_delay -clock [get_clocks usb3pipe_clk250] -max 2 [get_ports usb3h_RxDataK[*]]
set_input_delay -clock [get_clocks usb3pipe_clk250] -min 0 [get_ports usb3h_RxStatus[*]]
set_input_delay -clock [get_clocks usb3pipe_clk250] -max 2 [get_ports usb3h_RxStatus[*]]
set_input_delay -clock [get_clocks usb3pipe_clk250] -min 0 [get_ports usb3h_RxValid]
set_input_delay -clock [get_clocks usb3pipe_clk250] -max 2 [get_ports usb3h_RxValid]
set_input_delay -clock [get_clocks usb3pipe_clk250] -min 0 [get_ports usb3h_PowerPresent]
set_input_delay -clock [get_clocks usb3pipe_clk250] -max 2 [get_ports usb3h_PowerPresent]
set_input_delay -clock [get_clocks usb3pipe_clk250] -min 0 [get_ports usb3h_RxElecIdle]
set_input_delay -clock [get_clocks usb3pipe_clk250] -max 2 [get_ports usb3h_RxElecIdle]
set_output_delay -clock [get_clocks usb3tx_clk250] -min 0 [get_ports usb3h_RxPolarity]
set_output_delay -clock [get_clocks usb3tx_clk250] -max 1.6 [get_ports usb3h_RxPolarity]
set_output_delay -clock [get_clocks usb3tx_clk250] -min 0 [get_ports usb3h_RxTermination]
set_output_delay -clock [get_clocks usb3tx_clk250] -max 1.6 [get_ports usb3h_RxTermination]
set_output_delay -clock [get_clocks usb3tx_clk250] -min 0 [get_ports usb3h_Tx*]
set_output_delay -clock [get_clocks usb3tx_clk250] -max 1.6 [get_ports usb3h_Tx*]
set_output_delay -clock [get_clocks usb3tx_clk250] -min 0 [get_ports usb3h_PowerDown[*]]
set_output_delay -clock [get_clocks usb3tx_clk250] -max 1.6 [get_ports usb3h_PowerDown[*]]
set_output_delay -clock [get_clocks usb3tx_clk250] -min 0 [get_ports usb3h_Rate]
set_output_delay -clock [get_clocks usb3tx_clk250] -max 1.6 [get_ports usb3h_Rate]
set_output_delay -clock [get_clocks usb3tx_clk250] -min 0 [get_ports usb3h_reset_n]
set_output_delay -clock [get_clocks usb3tx_clk250] -max 1.6 [get_ports usb3h_reset_n]
set_output_delay -clock [get_clocks usb3tx_clk250] -min 0 [get_ports usb3h_ElasBufferMode]
set_output_delay -clock [get_clocks usb3tx_clk250] -max 1.6 [get_ports usb3h_ElasBufferMode]

 

 

 

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Participant
Participant
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Registered: ‎08-09-2020

the attachment is ti1310 tx/rx timing requirement.

timing.png
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Registered: ‎01-22-2015

@ha4456 

You appear to have a Source Synchronous Single Data Rate (SS-SDR) interface, with an interface clock frequency of 250MHz and a data-valid window that is 1ns wide.   This data-valid window is too small for static capture of the data.   That is, the Process-Voltage-Temperature (PVT) variations of properties for components inside the FPGA will cause the clock capture-edge to sometimes drift outside of the data-valid window.

Please see comments of avrumw about static capture limits in the following post.
https://forums.xilinx.com/t5/Timing-Analysis/set-input-delay-does-not-propagate-through-the-MMCM-PLL/m-p/1127122

In order to receive data from the ti1310, you will need to use dynamic capture methods which are described in Xilinx documents XAPP1017 and XAPP524.

Mark

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Participant
Participant
432 Views
Registered: ‎08-09-2020

hello Mark,

 

i just want to try a simple method by constrain(e.g: reducing net delay, select a near slice) before your method.

Your method is very good,however it needs time to redesign.

so,you can guide me how to fix my simple constrain according spec and report?

 

thanks

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