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Contributor
Contributor
474 Views
Registered: ‎12-20-2011

how to fix routing result

Hi, I have a dense designed consists three indentical cores in U200, each core works independently without any data transmission except adopting the same clock source. Each core is designed to place in each SLR. It is hard to meet timing in general implementation process. However, when we implement a design contains only one core that is constrained to one SLR, the timing is fine. 

In this case, we plan to run our design in three stages. First, a design called designA consists one core in SLR2 is impemented. Second, we plan to fix the LOC of each cells in designA and then add another core in SLR1. This design is called designB.  If designB is possible, then we can carry the same operations in final stage to routing the final core in the SLR0. 

The problem is that is it possible to do the second stage ? Any suggestion will help.

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Xilinx Employee
Xilinx Employee
387 Views
Registered: ‎06-27-2018

Hi @fanxitian,

Can you please explain, why do you want to do this in stages ? 

You can create 3 pblocks covering SLR0,1,2 separately and place 3 cores in each of them. Wouldn't this achieve same purpose ?

~Chinmay

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Moderator
Moderator
369 Views
Registered: ‎11-04-2010

Hi, @fanxitian ,

You can consider DFX flow. For the detailed information, please refer to UG909.

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Contributor
Contributor
310 Views
Registered: ‎12-20-2011

We have tried this method, timing closure can't be achieved under several implementation strategies. However, when we implement a design with one core constrained in one SLR,  the timing is fine. 

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Contributor
Contributor
307 Views
Registered: ‎12-20-2011

@hongh  Thanks, we will review this document and evaluate DFX flow.

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