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ssampath
Voyager
Voyager
561 Views
Registered: ‎10-12-2016

how to identify the exact route cause of module optimization in the opt_design stage ?

Hi Friends,

Am using vivado 2018.2. In elaboration am able to see a module which contains the ISERDES primitive. this is trimmed out after opt_design.

I tried opt_design in verbose mode, it is showing following mentioned WARNING but it's not clear . i cross checked all the inputs and outpus, connections are fine. in elaboration also am able to see all data and clock connections. i dont know why tool removing.

1) Is it possible to identify the exact route cause of module optimization in the opt_design stage ?

i want to see the log like:  {removed net/cell and its reason}.

Any help or suggestions are highly appreciated.

LOG:

WARNING: [Opt 31-163] Instance u_atlanta/u_pwd0_top/sarah_phy[0].u_fpga_rx_phy_2_1p4_port2_3/u_rx_phy/u_iserdes[0]/u_iserdes_s with type ISERDESE2 and SERDES_MODE=SLAVE will be removed because its outputs are unobservable. If the associated master SERDES requires the slave and is not removed, an error will be issued when generating the bitstream. To avoid this message and the removal of the slave SERDES (assuming it is needed by the master), please add a DONT_TOUCH property to it before running opt_design.
WARNING: [Opt 31-163] Instance u_atlanta/u_pwd0_top/sarah_phy[0].u_fpga_rx_phy_2_1p4_port2_3/u_rx_phy/u_iserdes[1]/u_iserdes_s with type ISERDESE2 and SERDES_MODE=SLAVE will be removed because its outputs are unobservable. If the associated master SERDES requires the slave and is not removed, an error will be issued when generating the bitstream. To avoid this message and the removal of the slave SERDES (assuming it is needed by the master), please add a DONT_TOUCH property to it before running opt_design.
WARNING: [Opt 31-163] Instance u_atlanta/u_pwd0_top/sarah_phy[0].u_fpga_rx_phy_2_1p4_port2_3/u_rx_phy/u_iserdes[2]/u_iserdes_s with type ISERDESE2 and SERDES_MODE=SLAVE will be removed because its outputs are unobservable. If the associated master SERDES requires the slave and is not removed, an error will be issued when generating the bitstream. To avoid this message and the removal of the slave SERDES (assuming it is needed by the master), please add a DONT_TOUCH property to it before running opt_design.
WARNING: [Opt 31-163] Instance u_atlanta/u_pwd0_top/sarah_phy[1].u_fpga_rx_phy_2_1p4_port2_3/u_rx_phy/u_iserdes[0]/u_iserdes_s with type ISERDESE2 and SERDES_MODE=SLAVE will be removed because its outputs are unobservable. If the associated master SERDES requires the slave and is not removed, an error will be issued when generating the bitstream. To avoid this message and the removal of the slave SERDES (assuming it is needed by the master), please add a DONT_TOUCH property to it before running opt_design.
WARNING: [Opt 31-163] Instance u_atlanta/u_pwd0_top/sarah_phy[1].u_fpga_rx_phy_2_1p4_port2_3/u_rx_phy/u_iserdes[1]/u_iserdes_s with type ISERDESE2 and SERDES_MODE=SLAVE will be removed because its outputs are unobservable. If the associated master SERDES requires the slave and is not removed, an error will be issued when generating the bitstream. To avoid this message and the removal of the slave SERDES (assuming it is needed by the master), please add a DONT_TOUCH property to it before running opt_design.
WARNING: [Opt 31-163] Instance u_atlanta/u_pwd0_top/sarah_phy[1].u_fpga_rx_phy_2_1p4_port2_3/u_rx_phy/u_iserdes[2]/u_iserdes_s with type ISERDESE2 and SERDES_MODE=SLAVE will be removed because its outputs are unobservable. If the associated master SERDES requires the slave and is not removed, an error will be issued when generating the bitstream. To avoid this message and the removal of the slave SERDES (assuming it is needed by the master), please add a DONT_TOUCH property to it before running opt_design.

-Sampath

-Sampath
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6 Replies
rshekhaw
Xilinx Employee
Xilinx Employee
538 Views
Registered: ‎05-22-2018

Hi @ssampath ,

I guess the Warning messages answers your all queries, like which instance are getting trimmed and why and also what can be done to avoid it.

Thanks,

Raj

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ssampath
Voyager
Voyager
530 Views
Registered: ‎10-12-2016

Hi @rshekhaw ,

what does meaning of "its outputs are unobservable" in the above log ? Currently am proceeding with that only as tool suggested.

-Sampath

-Sampath
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rshekhaw
Xilinx Employee
Xilinx Employee
430 Views
Registered: ‎05-22-2018

Hi @ssampath ,

 

""its outputs are unobservable"" means that the output of that specific instance is either unconnected or have some break in hierarchy.

Ti analyyze it you can open the schematic desifn and find that specific cell and chect the output pin of that instance on how it is passing in hierarchy.

And yes you can move ahead with don't_touch as it is a valid work around.

Thanks,

Raj

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ssampath
Voyager
Voyager
424 Views
Registered: ‎10-12-2016

Thank you@rshekhaw ,

Now i proceed with dont_touch and functionally its working. but my doubt is why tool is trimming.

i cross check all inputs and outputs,  all connections are looks good.

-Sampath

-Sampath
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rshekhaw
Xilinx Employee
Xilinx Employee
407 Views
Registered: ‎05-22-2018

Hi @ssampath ,

I have sent you a private message. Please check.

Thanks,

Raj

 

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rshekhaw
Xilinx Employee
Xilinx Employee
353 Views
Registered: ‎05-22-2018

Hi @ssampath 

Yes it is safe.

Also there may be n number of reasons for the trimming getting occured in your design and using Dont_touch is totally safe.

Thanks,

Raj.

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