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Visitor solamy
Registered: ‎11-11-2017

how to synchronize input and feedback signals in a closed loop

Hi guys, I was trying to implement a closed loop control  algorithm as figure below (I know it is really ugly). Now I have a concern on the synchronization between the input and feedback signals. Roughly, the transfer function of the system is y[n]=G*{x[n]-y[n-1]}. Since the feed forward path is complex, and it takes several system clocks to finish, (e.g. 10). Then, corresponding to input x[n], the output y[n] is obtained after 10 clocks, when the input signal is now x[n+10], and the feedback signal is still y[n-1]. The input signal x[n+10] is now not synchronized with the feed-back signal y[n-1] with regard to time. 


Are there methods with which the input and feed-back signals can be synchronized together? Or are there any way that the closed loop control algorithm can be realized alternatively? Thank you in advance. 



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Scholar markcurry
Registered: ‎09-16-2009

Re: how to synchronize input and feedback signals in a closed loop



What your describing is basically designing signal processing logic with a non-systemic clock - i.e. the processing clock is unrelated to the Sample clock.


What you need to do is some how encode or design in a representation of the sample interval.


One way to do this is to route a "data_enable" along with your data.  This pulse signal indicates when a new sample enters the pipeline.  Suitably delayed of "data_enable" could be pipelined along with your data - such that you have a "data_enable" at the output of G, (and elsewhere).


There's other methods too.  I actually struggle some times with good ways of describing / naming / diagramming the differences here.  I.e. one may have a FF in your data path that is for pipeliing only - i.e. to improve STA results.  Other FF's actually may represent the "Z-1" delay you have in typical signal processing diagrams. 


It's just key that when you do actually use / calculate all your values, that they are appropriately timed.  Sometimes I'm reduced to drawing out the pipeline by hand and labeling what's where in time (sometimes a spreadsheet helps).


It's key however to disassociate the "normal" synchronization task.  I.e. outside your diagram below, before the input you'd have some circuit that gathers the input data at Fs rates, and synchronized the signal to your processing clock.

Similar at the output side.   Then the entire processing datapath block will be fully synchronous to your processing clock.


Good luck.  I'm curious if others have their own strategies they'd like to share.





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