UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor fk5747
Visitor
261 Views
Registered: ‎03-26-2019

implement a part of VHDL code

Jump to solution

Hi,

I am working on a project which contanins two mainly block, the first one is a cross-corollation block which is working fine, and the second one is an ethernet module to send the data provided by cross-corollation to user. Currently, I am working on the Ethernet module. My question is, can I synthesize and implement the cross-corollation module and save it on FPGA (Artix7 evaluation kit), and each time I just need to implement the ethenet module? So I dont need to synthesize and implement whole the code which takes long time.

Thanks,

Regards

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
260 Views
Registered: ‎01-16-2013

Re: implement a part of VHDL code

Jump to solution

@fk5747 

 

Vivado Incremental compilation should be a good option for your case. Check the below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug904-vivado-implementation.pdf#page=97

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
2 Replies
Moderator
Moderator
261 Views
Registered: ‎01-16-2013

Re: implement a part of VHDL code

Jump to solution

@fk5747 

 

Vivado Incremental compilation should be a good option for your case. Check the below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug904-vivado-implementation.pdf#page=97

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
Scholar dpaul24
Scholar
248 Views
Registered: ‎08-07-2014

Re: implement a part of VHDL code

Jump to solution

@fk5747,

My question is, can I synthesize and implement the cross-corollation module and save it on FPGA (Artix7 evaluation kit), and each time I just need to implement the ethenet module? So I dont need to synthesize and implement whole the code which takes long time.

If I have understood correctly, there is an easy solution.

In the top module have a generic declared such as ENABLE_ETHERNET set to 0 to 1.

Then control the instiantiation of the Ethernet module as per generic value.

en_eth: if ENABLE_ETHERNET = '1' generate
  <instiantiate here>
else
  <drive all o/p signals to their default values>
end generate en_eth;

Whenever you want to synth your design, just change the value of the generic.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------