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Visitor
Visitor
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Registered: ‎03-26-2019

implement a part of VHDL code

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Hi,

I am working on a project which contanins two mainly block, the first one is a cross-corollation block which is working fine, and the second one is an ethernet module to send the data provided by cross-corollation to user. Currently, I am working on the Ethernet module. My question is, can I synthesize and implement the cross-corollation module and save it on FPGA (Artix7 evaluation kit), and each time I just need to implement the ethenet module? So I dont need to synthesize and implement whole the code which takes long time.

Thanks,

Regards

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Moderator
Moderator
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Registered: ‎01-16-2013

@fk5747 

 

Vivado Incremental compilation should be a good option for your case. Check the below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug904-vivado-implementation.pdf#page=97

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Moderator
Moderator
399 Views
Registered: ‎01-16-2013

@fk5747 

 

Vivado Incremental compilation should be a good option for your case. Check the below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug904-vivado-implementation.pdf#page=97

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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Scholar
Scholar
386 Views
Registered: ‎08-07-2014

@fk5747,

My question is, can I synthesize and implement the cross-corollation module and save it on FPGA (Artix7 evaluation kit), and each time I just need to implement the ethenet module? So I dont need to synthesize and implement whole the code which takes long time.

If I have understood correctly, there is an easy solution.

In the top module have a generic declared such as ENABLE_ETHERNET set to 0 to 1.

Then control the instiantiation of the Ethernet module as per generic value.

en_eth: if ENABLE_ETHERNET = '1' generate
  <instiantiate here>
else
  <drive all o/p signals to their default values>
end generate en_eth;

Whenever you want to synth your design, just change the value of the generic.

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