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Participant sum@
Participant
199 Views
Registered: ‎02-06-2019

implementation in verilog vivado

My code runs well in simulation and synthesis but when implimentation starts it gets stoped at opt_design and provide these errors

  • [Place 30-494] The design is empty Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.
  • [Common 17-69] Command failed: Placer could not place all instances

 

 

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4 Replies
Xilinx Employee
Xilinx Employee
189 Views
Registered: ‎05-22-2018

Re: implementation in verilog vivado

Hi sum@ ,

You are synthesizing/implementing the test bench file. Since this is a test bench file, you should not implement this module and use it only for Simulation. 

Also if you see your module code, there are no input and output ports.

For instance a verilog synthesizable module should be like :

module top(
  in_1      ,   in_2      ,  out     );
 input in_1, in_2 ;
 output out;
 wire out;
  assign out = a and b;
 
 endmodule 

Thanks,

Raj

Moderator
Moderator
171 Views
Registered: ‎11-04-2010

Re: implementation in verilog vivado

Hi, sum@  ,

You can run the below command in TCL CONSOLE to set the testbench file only used in Simulation as Raj suggested.

Ex:  set_property USED_IN simulation [get_files top_tb.v]

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Xilinx Employee
Xilinx Employee
165 Views
Registered: ‎02-27-2019

回复: implementation in verilog vivado

Hi sum@ ,

As mentioned , in your project , remove the top_tb.v and readd the file . When you add sources ,you will see below,choose Add or create simulation sources:

Capture.PNG

 

 

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Newbie delphine-14
Newbie
108 Views
Registered: ‎05-27-2019

回复: implementation in verilog vivado


@yangc wrote:

Hi sum@ ,

As mentioned , in your project , remove the top_tb.v and readd the file . When you add sources ,you will see below,choose Add or create simulation sources diebestetest

Capture.PNG

 

 


You can run the below command in TCL CONSOLE to set the testbench file only used in Simulation as Raj suggested.

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