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Observer jacklsw86
Observer
3,005 Views
Registered: ‎07-26-2012

incomplete i/o assignment for differential pins in planahead

i am using planahead from ISE 14.2 to assign I/O pins. I think there is a bug in planahead when assigning differential pins. from the GUI, when i select a site for a port, the differential pair is automatically LOC-ed. However when I close and save constraint file in Planahead and implement it back in ISE, I noticed that some of the differential pins are missing from the assignment (incomplete).

 

does anyone else encounters the same thing?

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2 Replies
Xilinx Employee
Xilinx Employee
2,990 Views
Registered: ‎07-01-2008

Re: incomplete i/o assignment for differential pins in planahead

For a PlanAhead solution I suggest taking this question to the Design Planning forum. For an Implementation tool solution you can just add the necessary UCF constraint manually.

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Observer jacklsw86
Observer
2,979 Views
Registered: ‎07-26-2012

Re: incomplete i/o assignment for differential pins in planahead

thanks bwade, i'll forward the question to that forum instead.

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