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Explorer
Explorer
3,099 Views
Registered: ‎01-18-2011

invisible pll phase change

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Hello

 

I use Vivado 2016.4 and xcku095-ffvb1760-1c FPGA. I open implemented design and execute next tcl commands to get the first bit-file:

set_property CLKOUT0_PHASE 180.000 [get_cells cm/dmc_pll/pll_base_gen.PLLE3_BASE_inst]

write_checkpoint -force d:/Project/.../topSL_lvcmos_routed.dcp

reset_run impl_8 -prev_step

launch_runs impl_8 -to_step write_bitstream -jobs 2

 

Then I execute next tcl commands to get the second bit-file with another CLKOUT0_PHASE:

set_property CLKOUT0_PHASE 270.000 [get_cells cm/dmc_pll/pll_base_gen.PLLE3_BASE_inst]

write_checkpoint -force d:/Project/.../topSL_lvcmos_routed.dcp

reset_run impl_8 -prev_step

launch_runs impl_8 -to_step write_bitstream -jobs 2

 

But both bit-files are identical except date! What is the reason of this? Checkpoints and bit-files attached.

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Explorer
Explorer
4,841 Views
Registered: ‎01-18-2011

Re: invisible pll phase change

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Bit-files are identical because valid phase shifts are in 360 / CLKFBOUT_MULT = 360 / 3 = 120 degree increments. Phase 180 and phase 270 are not possible in this case. DRC not find this violation in the 2016.4.

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Xilinx Employee
Xilinx Employee
3,076 Views
Registered: ‎02-14-2014

Re: invisible pll phase change

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Hello @taganrog,

 

When I am running below command after opening both checkpoints I am getting expected values. 

get_property CLKOUT0_PHASE [get_cells cm/dmc_pll/pll_base_gen.PLLE3_BASE_inst]

 

For first run this command returns 180.000 and for second run, it returns 270.000

So can you share evidence where you observe that difference is not present? Have you tried checking this phase shift on hardware?       

 

Regards,
Ashish
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Explorer
Explorer
3,067 Views
Registered: ‎01-18-2011

Re: invisible pll phase change

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Hello ashishd,

 

I observe it after comparing bit-files by content in the Total Commander. I attached screenshot.

I haven't  tried checking this phase shift on hardware. It is not possible for a while.

 

 
1.jpg
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Explorer
Explorer
4,842 Views
Registered: ‎01-18-2011

Re: invisible pll phase change

Jump to solution

Bit-files are identical because valid phase shifts are in 360 / CLKFBOUT_MULT = 360 / 3 = 120 degree increments. Phase 180 and phase 270 are not possible in this case. DRC not find this violation in the 2016.4.

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