10-16-2013 08:15 AM
I want to use bidrectional data bus of 32 bits in spartan 6 (lx25) (tool use : ISE 14.1). For this , I have used following code. FPGA is slave device here.
component IOBUF is
CAPACITANCE : string := "DONT_CARE";
DRIVE : integer := 12;
IBUF_DELAY_VALUE : string := "0";
IBUF_LOW_PWR : boolean := TRUE;
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "DEFAULT";
SLEW : string := "SLOW"
O : out std_ulogic;
IO : inout std_ulogic;
I : in std_ulogic;
T : in std_ulogic
Problem: In chipscope, the bus holds some garbage value rather than the value master drives(writing to FPGA).
a) Is it bus contention?
b) Do I have to change the attributes according the master device's IO specification (like drive current, voltage, capacitance,slew etc)?
c) Do I need to give constriants for pull up/ pull down for data bus?
Note : The bus is holding value correctly during read operation by Master(PEX 8311) (i.e, when FPGA is driving the bus).
10-16-2013 08:36 AM - edited 10-16-2013 08:39 AM
a)How do you connect Chipscope core to your input? Directly? Do you have OFFSET IN constraints applied?
It seems one timing issue.
For b) and c), the Spartan® Family FPGAs board is more suitable.
10-16-2013 10:35 AM
To see the input, io bus is assigned to the signal in clock process.
elsif (rising_edge(master_cllk)) then
data_bus_reg <= io_bus;
a) To see in chipscope, data_bus_reg is mapped. I have not used any "offset in" constraint. What kind of timing issue??
b) and c) spartan 6 is intergrated in custom board.
10-16-2013 07:24 PM
You asked if this might be bus contention. What is going on with the T input to the BUFIO when you are receiving data into the FPGA? T should be high to disable the output drive of the FPGA. It should be easy enough to add the T signal to your ChipScope if it isn't already there.
10-16-2013 08:15 PM
To sample io_bus by data_bus_reg correctly, the setup and hold time requirement of data_bus_reg must be met. To check the timing, tools need to know the phase relationship between io_bus and master_clk. Thus, OFFSET IN constraints is needed. You may refer to UG625.
For the board, sorry that I mean the discussion board: Xilinx User Community Forums -> Xilinx Products -> Silicon Devices -> Spartan Family FPGAs.
10-16-2013 11:05 PM
10-16-2013 11:31 PM