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tvgod2000
Observer
Observer
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Registered: ‎07-27-2018

is there a way to prevent OBUF from being mapped automatically, even if the variable is declared OUTPUT when coding?

Hi!

I am using ISE and I am using Verilog And I use Spartan6 SP605.

I'd like to ask you, is there a way to prevent OBUF from being mapped automatically, even if the variable is declared OUTPUT when coding?

What I want to do is to act as OUTPUT, but I don't want to do mapping and I want to see the results in P&R Simulation(about output).

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blindobs
Adventurer
Adventurer
447 Views
Registered: ‎09-13-2018

look for verilog attributes

(*dont_touch = "true"*)
(* KEEP = "TRUE" *)

 for keeping registers from being removed from synthesis tool if their output doen't drive any module output

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