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Registered: ‎01-05-2017

kc705 conflicting iostandard

Hi guys,



This what I have with my design. I'm trying to send serial data through FMC HPC connector on a kc705 evaluation board. As an input I read the 8 bits from 4 dip switch + 4 pushbutton. Then serializing the data and sending out... Just playing with this connector and general structure of making a design for an FPGA


[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 22 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk_out.


What I understand there is something wrong with the iostandard voltage values. Then I wrote down the bank I used for the design, in brief they are


LED(0-3) : Bank 33   HP

LED (4)   : Bank 13   HR

LED(5-6) : Bank 17   HR

LED(7)    : Bank 18   HR


data_in(0-3) : Bank 13   HR

data_in(4)    : Bank 18   HR

data_in(5)    : Bank 34    HP

data_in(6-7) : Bank 33   HP


system_clock : Bank 33  HP


start_view  : Bank 17   HP

stop_view  : Bank 17   HP

data_out    : Bank 17   HP


What I understand is there are limitaitons on HR / HP bank types and even for each bank and LED and system clock must have the same or similar iostandard property. I've searched on the internet for finding a document related to iostandard properties of banks. If even I found, I didn't understand it so far. Could you please make a explanation or just correct the constraitn file?


I'll appreciate it!

Thanks in advance






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3 Replies
Registered: ‎02-27-2008

Are you sure your constraints file is in your project?


Look at the log.  Pay attention to any earlier messages.  Is there another xdc constraints file over-riding the one you posted?

Austin Lesea
Principal Engineer
Xilinx San Jose
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Registered: ‎01-23-2009

The tools are telling you (correctly) that there is one top level signal from your design that you have not applied an IOSTANDARD (nor a PACKAGE_PIN) to. This lets the tools choose any location and use the "DEFAULT" IOSTANDARD for the pin. The DRC flags this as an violation, since it is generally not legal to put a design in this configuration on a board.


Your design has the port "clk_out" for which there is no corresponding constraints in the .xdc file...



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Registered: ‎01-05-2017


Thank you for the answers. I fixed the problem. I was thinking about a more complicated solution but ok sometimes this happens. 


in between I want to ask about a warning i'm having when I declare system clock on kc705. LEDs and system clock are both on bank 33 and when I use master xdc file info it gives error. if they use different IOstandard why they are on the same bank and why don't accept the master file info (LVDS for clock)? You may see that I used  " DIFF_SSTL15 " and it works with a warning:


[DRC 23-20] Rule violation (PORTPROP-2) selectio_diff_term - The port clk_in_n has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_SSTL15 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.



If some one give the correct definition this will be very helpful. 


Thanks in advance!



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