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Explorer
Explorer
8,928 Views
Registered: ‎05-03-2012

limit route_design iterations

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Hi All

 

please help to limit route_design iterations till exit

 

in 2015.3 only directives are described in User Guide (dont help)

 

in conguestion case I need to wait hours before see conflicts

 

Thank you

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1 Solution

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Community Manager
Community Manager
16,849 Views
Registered: ‎06-14-2012

Re: limit route_design iterations

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There is no way to decrease the number of route iterations. The tool does its best to meet your requirements and eoute it sucessfully.

You can do report_design_analysis -congestion to get some congestion statistics.

 

 

Regards

Sikta

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8 Replies
Explorer
Explorer
8,923 Views
Registered: ‎04-28-2015

Re: limit route_design iterations

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Hi @mikerez

 

Please check if 'incremental place and route' helps in your case.
Page 34 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_4/ug904-vivado-implementation.pdf

 

Thanks,

Tushar.

 

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Xilinx Employee
Xilinx Employee
8,906 Views
Registered: ‎10-24-2013

Re: limit route_design iterations

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Hi @mikerez

 

You can also refer to the video for quick reference.

http://www.xilinx.com/training/vivado/using-incremental-implementation-in-vivado.htm

 

The following document has a lab (lab-2) which explains the procedure with example design.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug986-vivado-tutorial-implementation.pdf

Thanks,Vijay
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Explorer
Explorer
8,894 Views
Registered: ‎05-03-2012

Re: limit route_design iterations

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how incremental compilation could help limiting route_design iterations??

 

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Community Manager
Community Manager
16,850 Views
Registered: ‎06-14-2012

Re: limit route_design iterations

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There is no way to decrease the number of route iterations. The tool does its best to meet your requirements and eoute it sucessfully.

You can do report_design_analysis -congestion to get some congestion statistics.

 

 

Regards

Sikta

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Moderator
Moderator
8,760 Views
Registered: ‎01-16-2013

Re: limit route_design iterations

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@mikerez,

 

You can use Flow_RuntimeOptimized implementation strategy  to reduce the iterations. Please check page number 153 in below Implementation user guide:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug904-vivado-implementation.pdf

 

--Syed

 

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Did you check our new quick reference timing closure guide (UG1292)?
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Moderator
Moderator
8,759 Views
Registered: ‎01-16-2013

Re: limit route_design iterations

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@mikerez,

 

If you want to limit iteration only on route_design then use the directive "RuntimeOptimized". Check page number 79 in same above User guide.

 

--Syed

 

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Explorer
Explorer
8,745 Views
Registered: ‎05-03-2012

Re: limit route_design iterations

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no this dont impact iterations count

the answer is found

 

ps.  so many false answers from moderators and Xilinx employees, is it a big game for kudos?

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Community Manager
Community Manager
8,734 Views
Registered: ‎06-14-2012

Re: limit route_design iterations

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@mikerez I think there was some confusion with runtime and phase iterations of the route process. So there were some incorrect pointers.

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