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Observer applefat
Observer
9,551 Views
Registered: ‎01-29-2012

map fails to integrate hard macro

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Hello--

 

I'm using a spartan 6 device under ISE12.2. I created a small hard macro using fpga editor. It is VERY small, literally a single slice with an external route I want to keep. I followed these steps as suggested in xilinx docs--

 

1) export routed design as nmc

2) unplace pads

3) add external macro pins to the slice pins that used to be routed to the pads

4) copy the nmc into my project directory

 

Then I use the component like any other--I instantiate it ONCE for testing. ISE systhesis tools finds the nmc, everything goes smoothly without error or warning until global map (phase 11.8).  Then the tool errors, saying that the design cannot be mapped, because it either doesn't fit or is too complicated. But the rest of my project isn't even close to filling the fpga, and the macro is literally 1 slice. How can this be?

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Xilinx Employee
Xilinx Employee
9,179 Views
Registered: ‎07-01-2008

Re: map fails to integrate hard macro

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I used your existing NGC and NMC files and I was able to get this to work by adding a UCF LOC constraint:

INST i0 LOC =SLICE_X0Y2;

 

I was also able to place the macro manually in FPGA Editor. The bug is just that auto-placement can't handle the macro. I see that you never defined a reference comp for the macro. That doesn't seem to matter for this single component case. For a larger macro you'll probably need to do that to LOC it successfully

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16 Replies
Xilinx Employee
Xilinx Employee
9,545 Views
Registered: ‎06-11-2009

Re: map fails to integrate hard macro

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You may refer the following AR . This is quite informative and helpful.

http://www.xilinx.com/support/answers/10901.htm

 

Whats the exact error message? Could you try it in the latest tools 13.4?

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Xilinx Employee
Xilinx Employee
9,538 Views
Registered: ‎07-01-2008

Re: map fails to integrate hard macro

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It sounds like a reference component wasn't defined for the macro. Select the slice, then Edit-->Set Hard Macro Reference Comp.

 

What is the reason for using a hard macro in the first place? I don't know of  anything that can be done with a single slice that wouldn't be much easier to do with an RPM macro and appropriate pack/place constraints.

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Observer applefat
Observer
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Registered: ‎01-29-2012

Re: map fails to integrate hard macro

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siktapany, that's the link I was following. However, I admit there was something strange.  So, after deleting the pads, dots appear on the slice pins as described. Then I delete the unrouted nets,  and it actually unroutes the connections inside the slice! So it breaks the design, in fact after removing them it doesn't even pass DRC. It does pass DRC when I leave the unrouted Nets. I must be misunderstanding something there. As a result, I left the unrouted nets. I don't know if that's part of the problem...

 

I will get the exact error for you as soon as I get to my machine....

 

bwade,  I can try that.  As for why-- inside the slice, I use two LUTs. A single net comes out of the slice, out to the switch matrix, and back to the slice (to the other LUT). I want those two LUTS to always be in the same positions, and the route to always be exactly the same.  If I let synthesis do whatever it wants, sometimes it splits the LUTs, and the routing is never the same. Given these constraints can it still be done with out hard macros?

 

Thanks guys

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Xilinx Employee
Xilinx Employee
9,529 Views
Registered: ‎07-01-2008

Re: map fails to integrate hard macro

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You can instantiate LUTs to ensure that they always exist post-synthesis. Use LOCK_PINS constraints to both control the pin usage and prevent map from optizing the LUTs away. Use BEL constraints to define the BEL location within the slice (A6LUT, A5LUT, etc,). Use RLOC constraints to define relative slice location within macro or use LOC to define a fixed slice position. Use RLOC_ORIGIN to define a fixed macro position. Use XBLKNM if needed to exclude other logic from the slice by applying XBLKNM to all logic that is included. Use Directed Routing constraints to control the routing. Not all of this is necessary, depending on your use case.

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Observer applefat
Observer
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Registered: ‎01-29-2012

Re: map fails to integrate hard macro

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Ok. I have been having some success using the regular constraints. Thank you for that! I really value your input.

 

I would still really like to know how to make a macro, if only to have it available as an option. It's something several of my labmates have not been able to do either, and it really doesn't seem like it should be so difficult, especially since others have succeeded.  A few points. This is a step in the provided Xilinx instructions:

 

"7. Delete the un-placed pads and un-routed nets from your list window by selecting the un-placed or un-routed components in the list window and click the Delete button (located near the right side of the FPGA Editor window)."

 

But as I mentioned, when unrouted nets are deleted, it unroutes any connections INSIDE the slice having the same name. So it breaks the macro.  If I regenerate these internal slice routes, they are just marked as unrouted again. What's the idea? Furthermore, I noticed in earlier versions of fpga editor, external pins would be marked solid green. But in 12.2 they are forever marked with that suspicious blue dot.

 

Another point--the following is my macro instantiation:

 

M1:my_macro port map(clk=>clk, rst=>rst, q1=>t1, q2=>t2);

 

I get warning:

 

WARNING:HDLCompiler:634 - Line 60: Net <t1> does not have a driver.
WARNING:HDLCompiler:634 - Line 61: Net <t2> does not have a driver.

 

q1 and q2 are marked as external output pins in the macro. There is no error saying that they can't be found, but apparently they are not driving, even though they directly connect to a pair of DFF in the slice? My macro has no DRC errors or warnings.

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
9,501 Views
Registered: ‎07-01-2008

Re: map fails to integrate hard macro

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Deleting a net shouldn't have any affect on the component configuration. The only visible change in Logic Block Editor should be that no net name is displayed on the pin which would be normal. You should still see the configured paths hi-lighted in blue. You can also compare config strings before and after by selecting the component and hitting the info or attribute button.

 

The blue dot is just a one-node net. You can examine the external pins through the list window if you can't find them visually.

 

Make sure that the macro has a driver configured for the output external pins.

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Observer applefat
Observer
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Registered: ‎01-29-2012

Re: map fails to integrate hard macro

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bwade, please see the attached screenshot. The red box is the configuration before deleting the unrouted net "clk", and the blue box is the configuration for the same component after deleting it.

screen.png
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Xilinx Employee
Xilinx Employee
9,489 Views
Registered: ‎07-01-2008

Re: map fails to integrate hard macro

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This looks like a bug. You can maybe restore the original configuration by running the command:

setattr comp Q2_OBUF config "original config string"

You will need to quote the config string.

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Observer applefat
Observer
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Registered: ‎01-29-2012

Re: map fails to integrate hard macro

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Ok. Then,  is removing these unrouted nets strictly necessary? Can it cause problems?

 

I finally did get back to the mapping error, here goes. I'm only trying to add one instance. Besides the error itself what's also strange is that it claims there are 8LUT and 8 FF in my macro instance "G1",  when the macro design contains a single slice using 2LUTS, 2FF:

 

------------------------

Phase 12.9  Local Placement Optimization
ERROR:Place:543 - This design does not fit into the number of slices available
   in this device due to the complexity of the design and/or constraints.

   Unplaced instances by type:

     LUT    8 (5.4)
     FF    8 (6.6)

   Please evaluate the following:

   - If there are user-defined constraints or area groups:
     Please look at the "User-defined constraints" section below to determine
     what constraints might be impacting the fitting of this design.
     Evaluate if they can be moved, removed or resized to allow for fitting.
     Verify that they do not overlap or conflict with clock region restrictions.
     See the clock region reports in the MAP log file (*map) for more details
     on clock region usage.

   - If there is difficulty in placing LUTs:
     Try using the MAP LUT Combining Option (map lc area|auto|off).

   - If there is difficulty in placing FFs:
     Evaluate the number and configuration of the control sets in your design.

 the last set of instances that failed to place:

   0. Placer RPM (size: 16)
      LUT Puf_circuit0/G1/puf
      LUT Puf_circuit0/G1/tri1
      LUT Puf_circuit0/G1/puf
      LUT Puf_circuit0/G1/tri2
      LUT Puf_circuit0/G1/puf
      LUT Puf_circuit0/G1/puf
      LUT Puf_circuit0/G1/puf
      LUT Puf_circuit0/G1/puf
      FF Puf_circuit0/G1/puf
      FF Puf_circuit0/G1/FDCE_inst1
      FF Puf_circuit0/G1/puf
      FF Puf_circuit0/G1/FDCE_inst2
      FF Puf_circuit0/G1/puf
      FF Puf_circuit0/G1/puf
      FF Puf_circuit0/G1/puf
      FF Puf_circuit0/G1/puf

ERROR:Place:120 - There were not enough sites to place all selected components.

Phase 12.9  Local Placement Optimization (Checksum:ebdafc8e) REAL time: 1 mins 34 secs

Total REAL time to Placer completion: 1 mins 34 secs
Total CPU  time to Placer completion: 1 mins 22 secs
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
--------------------------------------------

The map summary is shown below just to show that the FPGA is not even close to being filled, even if all those 16 components actually needed to be mapped:

 

Interim Summary
---------------
Slice Logic Utilization:
  Number of Slice Registers:                   116 out of  54,576    1%
    Number used as Flip Flops:                 116
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                        180 out of  27,288    1%
    Number used as logic:                      176 out of  27,288    1%
      Number using O6 output only:              96
      Number using O5 output only:              48
      Number using O5 and O6:                   32
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   6,408    0%
    Number used exclusively as route-thrus:      4
      Number with same-slice register load:      0
      Number with same-slice carry load:         4
      Number with other load:                    0

Slice Logic Distribution:
  Number of LUT Flip Flop pairs used:          193
    Number with an unused Flip Flop:            82 out of     193   42%
    Number with an unused LUT:                  13 out of     193    6%
    Number of fully used LUT-FF pairs:          98 out of     193   50%
    Number of unique control sets:              11
    Number of slice register sites lost
      to control set restrictions:              44 out of  54,576    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                        11 out of     218    5%
    Number of LOCed IOBs:                       11 out of      11  100%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         1 out of     116    1%
  Number of RAMB8BWERs:                          1 out of     232    1%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       2 out of      16   12%
    Number used as BUFGs:                        2
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       8    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     376    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     376    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     256    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      58    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       4    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

  Number of hard macros:           1

 

 

-----------------------------

Finally, I also tried to add the macro in fpga editor. I know that the component uses a SLICEX, so I selected a SLICEX and then clicked "Add hard macro instance". The editor failed to add it. The history text box is shown below as the macro is loaded:

 

site "SLICE_X27Y64",  type = SLICEX  (RPM grid X71Y256)
Getting available speed grades of the device...
   "C:\Users\ajmills\Desktop\puf\mypuf\puf_single" is an NCD, version 3.2, device xc6slx45, package csg324, speed -3
   "C:\Users\ajmills\Desktop\puf\mypuf\puf_single" is an NCD, version 3.2, device xc6slx45, package csg324, speed -3
add hm "C:\Users\ajmills\Desktop\puf\mypuf\puf_single.nmc" a
WARNING:FPGAEditor:696 - Cannot place hard macro "a" at site "SLICE_X27Y64" -- The route patterns of internal networks cannot be replicated.
WARNING:FPGAEditor:629 - Cannot place hard macro "a" at site "SLICE_X27Y64"
Added macro "a".

 

 

 

Thank you

 

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Observer applefat
Observer
6,360 Views
Registered: ‎01-29-2012

Re: map fails to integrate hard macro

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I created another circuit, even more basic. It's just a single LUT with an input and an output. When I try to instantiate this, I get the following:

 

ERROR:Place:835 - Given the original pre-placement, no legal placements can be
   found for 1 group(s). The following is the description of these group(s). The
   relative offsets of the components are shown in brackets next to the
   component names.
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)


My code for the entire macro is below:

 


entity top is
    port(
        x: in std_logic;
        q: out std_logic
        );
end top;

architecture Behavioral of top is

    signal t: std_logic;

    attribute lock_pins: string;
    attribute lock_pins of tri2 : label is "all";


begin

tri2 : LUT5
generic map (
INIT => X"55555555") -- Specify LUT Contents
port map (
O => t, -- LUT general output
I0 => x, -- LUT input
I1 => '0', -- LUT input
I2 => '0', -- LUT input
I3 => '0', -- LUT input
I4 => '0' -- LUT input
);

q<=t;

end Behavioral;


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Xilinx Employee
Xilinx Employee
6,354 Views
Registered: ‎07-01-2008

Re: map fails to integrate hard macro

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Are you setting the slice as the reference comp? Can you attach the macro along with your other source in a zip file?

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Observer applefat
Observer
6,348 Views
Registered: ‎01-29-2012

Re: map fails to integrate hard macro

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I did set that.

 

Attached is a project for my target device. It is the simplest test I can think of, but it also did not synthesize.

 

Three important files:

top.vhd--file that instanciates the macro

puftest.vhd--file from which the macro was created

puftest.nmc--the macro file I created

 

Thanks bwade for taking a look.

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Xilinx Employee
Xilinx Employee
9,180 Views
Registered: ‎07-01-2008

Re: map fails to integrate hard macro

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I used your existing NGC and NMC files and I was able to get this to work by adding a UCF LOC constraint:

INST i0 LOC =SLICE_X0Y2;

 

I was also able to place the macro manually in FPGA Editor. The bug is just that auto-placement can't handle the macro. I see that you never defined a reference comp for the macro. That doesn't seem to matter for this single component case. For a larger macro you'll probably need to do that to LOC it successfully

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Observer applefat
Observer
6,338 Views
Registered: ‎01-29-2012

Re: map fails to integrate hard macro

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Ah yeah, it works now, it was just the missing LOC. In retrospect, it's clear why that should be necessary, especially for very large macros. If it's essential though, in the future maybe a note should be added to the Xilinx reference page, for others....

 

One last question. I did set the reference comp in fpga_editor. Is there a code constraint you were looking for?

 

Thanks a lot for your help!

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Xilinx Employee
Xilinx Employee
6,335 Views
Registered: ‎07-01-2008

Re: map fails to integrate hard macro

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You define the reference comp in the editor. A circle will then appear in that comp. Maybe you just didn't save that version. There's no reason the placer can't handle the macro. I've filed a CR for the placer bug.

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495 Views
Registered: ‎05-24-2019

Re: map fails to integrate hard macro

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I have a similar error : Given the original pre-placement, no legal placements can be
found for 1 group(s). The following is the description of these group(s). The
relative offsets of the components are shown in brackets next to the
component names.

 

I am using Artix7 XC7A100T-csg324 , I tried adding  INST i0 LOC =SLICE_X0Y147; in my .ucf file however I am still getting the error. Can some one please help

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