09-11-2019 05:09 AM
WARNING:MapLib:701 - Signal rx connected to top level port rx has been removed.
i am getting warring message like this here rx i am using as input thiss input i connected through the onther module . i would have three modules i take the rx pin in top module i connected this pin input to the other sub module.
what i am trying to do is uart communication between the fpga and pc.
below i mention the related verilog files please any body go through my code and try to help me to resolve this thing..
where iam using spartan -3e and xilinx ise tool .
09-12-2019 02:48 AM
Add the RTL file for module/primitive fifo which is defined in top module.
09-12-2019 11:03 PM
09-14-2019 03:51 AM
you didn't assign r_Tx_DV20 signal Wr_en signal of your FIFO,
firstly test your code without FIFO by only capturing your rx signal and show it on ILA, and then make change step by step.
09-14-2019 11:37 AM
I have checked your code twice, Please recheck wr_en of your FIFO, It seems that this signal is tied to 0 and noting write on the FIFO.
you should check your code without FIFO at first then put the FIFO inside your design to be confident that nothing is being deleted by the synthesizer.
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