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391 Views
Registered: ‎02-11-2019

map issues

Hello...

WARNING:MapLib:701 - Signal rx connected to top level port rx has been removed.

i am getting warring message like this here rx i am using as input thiss input i connected through the onther module . i would have three modules i take the rx pin in top module i connected this pin input to the other sub module.

what i am trying to do is uart communication between the fpga and pc.

 below i mention the related verilog files please any body go through my code and try to help me to resolve this thing..

where iam using spartan -3e and xilinx ise tool .

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6 Replies
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Explorer
Explorer
350 Views
Registered: ‎03-16-2019

it seems like that you haven't assigned a pin to your RX signal in the XDC file.

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Moderator
Moderator
343 Views
Registered: ‎01-16-2013

tnareshnaresh7@gmail.com 

 

Add the RTL file for module/primitive fifo which is defined in top module.

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Highlighted
324 Views
Registered: ‎02-11-2019

i added the pin number for the RX signal i don't know where could be the issues
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322 Views
Registered: ‎02-11-2019

i just take an fifo ip from the xilinx ip cores. then how would i addRTL file for module/primitive fifo which is defined in top module
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Explorer
Explorer
250 Views
Registered: ‎03-16-2019

you didn't assign r_Tx_DV20 signal Wr_en  signal of your FIFO, 

firstly test your code without FIFO by only capturing your rx signal and show it on ILA, and then make change step by step.

 

 

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Explorer
Explorer
289 Views
Registered: ‎03-16-2019

I have checked your code twice, Please recheck wr_en of your FIFO, It seems that this signal is tied to 0 and noting write on the FIFO. 

you should check your code without FIFO at first then put the FIFO inside your design to be confident that nothing is being deleted by the synthesizer.

 

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