cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
avinashc
Explorer
Explorer
425 Views
Registered: ‎10-09-2018

mig 7 series- error ngdbuild 455

Hello,

system- Artix 7, ISE 14.7, Win10

I am using MIG IP core for ddr3 and i am using example design. I am getting this error as below

pll_inst1 : pll
port map
(-- Clock in ports
CLK_IN1 => sys_clk_i,--CLK_IN1, pll_clk
-- CLKFB_IN => CLKFB_OUT,--CLKFB_IN,
-- Clock out ports
CLK_OUT1 => CLK_OUT1_s, ---400 MHz
CLK_OUT2 => CLK_OUT2_s, ---200 MHz
-- CLKFB_OUT => CLKFB_OUT,
-- Status and control signals
RESET => pll_rst,
LOCKED => LOCKED);




ERROR:NgdBuild:455 - logical net 'CLK_OUT2_s' has multiple driver(s): pin CLKOUT1 on block pll_inst1/plle2_adv_inst with type PLLE2_ADV, pin PAD on block CLK_OUT2_s with type PAD

If I give separate clk to sys_clk & ref_clk then it works fine(no error), but ass soon as I use pll for 2nd output to ref_clk, I am getting this error.

tried with no buffer ,bufg in the output of pll. This CLK_OUT2_s is not used anywhere in logic.

why it is giving multiple driver error?

0 Kudos
1 Reply
syedz
Moderator
Moderator
293 Views
Registered: ‎01-16-2013

@avinashc 

 

Open synthesized design and check the connection of net mentioned in error message "CLK_OUT2_s"

The error is complaining that this net is driven by two or more drivers.

 

Also check this related forum link: 
https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/NgdBuild-455-Multiple-drivers-error-related-with-DDR2-clocking/m-p/484152 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos