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Voyager
Voyager
1,318 Views
Registered: ‎10-12-2016

net routable but not routed ?

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Hi Friends,

Am using xc2000T,

Tool showing route status as : net routable but not routed ?

rx1_tx2_unrote_status.png

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Historian
Historian
1,070 Views
Registered: ‎01-23-2009

Re: net routable but not routed ?

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To be a bit clearer...

Yes, there are physical limitations as to how many clock signals (signals on clock nets) can be used as data pins of CLBs. The reason that this limitation is generally not a problem is that you should not be using clocks as data.

A clock should only be used to clock clockable cells - they should go directly to the C port of flip-flops in the slice, the IOB flip-flops, the ISERDES/OSERDES. the block RAMs, the DSPs, the distributed RAMs, but not to the D (or CE) pin of flip-flops or the data pins of LUTs or RAMs or anything else. With a small number of exceptions, doing this is usually "bad design".

So you need to look at your source and figure out how/why you are using a clock as a data signal and fix the RTL code to not do that...

Avrum

19 Replies
Xilinx Employee
Xilinx Employee
1,296 Views
Registered: ‎06-27-2018

Re: net routable but not routed ?

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Hi  @ssampath,

Can you please provide route status report (run report_route_status from tcl console) generated after route_design. Open implemented schematic, right click on that net and select route, check what error you get.

Thanks,

Chinmay

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Voyager
Voyager
1,287 Views
Registered: ‎10-12-2016

Re: net routable but not routed ?

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Route_status_jan20_2PM.PNG
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Voyager
Voyager
1,286 Views
Registered: ‎10-12-2016

Re: net routable but not routed ?

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Route_status2_jan20_2PM.PNG

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Scholar drjohnsmith
Scholar
1,241 Views
Registered: ‎07-09-2009

Re: net routable but not routed ?

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Are you really using a xc2000T
what tools are you using
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Moderator
Moderator
1,232 Views
Registered: ‎01-16-2013

Re: net routable but not routed ?

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@ssampath

 

Share the vivado.log (for non-project mode) or runme.log (project mode). If possible, can you share  the post routed dcp as well?

Here is general AR on debugging routing error:

https://www.xilinx.com/support/answers/53854.html

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Voyager
Voyager
1,198 Views
Registered: ‎10-12-2016

Re: net routable but not routed ?

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Hi ,

 

route_design -nets [get_selected_objects ]
Command: route_design -nets {{u_atlanta/u_pwd0_top/tx_fpll[0].u_tx_fpll/fpga_int_pll_on.u_pll/tx_fpll_ckout[0]}}
Attempting to get a license for feature 'Implementation' and/or device 'xc7v2000t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7v2000t'
INFO: [Common 17-1540] The version limit for your license is '2018.03' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Interactive Router Task

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 7a06a4df

Time (s): cpu = 00:04:00 ; elapsed = 00:01:27 . Memory (MB): peak = 17025.113 ; gain = 90.551 ; free physical = 49145 ; free virtual = 501854
INFO: [Route 35-47] Routing for 1 net will be attempted.
Post Restoration Checksum: NetGraph: 8e2cab10 NumContArr: 4c08525c Constraints: 0 Timing: 0

Phase 2 Router Initialization
Phase 2 Router Initialization | Checksum: d213ae5b

Time (s): cpu = 00:04:26 ; elapsed = 00:01:48 . Memory (MB): peak = 17025.113 ; gain = 90.551 ; free physical = 48993 ; free virtual = 501715
 Number of Nodes with overlaps = 0
CRITICAL WARNING: [Route 35-276] Interactive router failed to route 1  net.
Resolution: Run report_route_status and review the logfile to identify routing failures.

Unroutable connection Types:
----------------------------
Type 1 : BUFGCTRL.O->SLICEL.A6
-----Num Open nets: 1
-----Representative Net: Net[43] u_atlanta/u_pwd0_top/tx_fpll[0].u_tx_fpll/fpga_int_pll_on.u_pll/tx_fpll_ckout[0]
-----BUFGCTRL_X0Y29.O -> SLICE_X327Y149.A6
-----Driver Term: u_atlanta/u_pwd0_top/tx_fpll[0].u_tx_fpll/fpga_int_pll_on.u_pll/clk_buf.u_clk_output0_buf/O Load Term [40568]: u_atlanta/u_pwd0_top/u_pwd0_clk_gen/u_atlanta_pwd_clk_gen/u_fpga_clk_through_lut0/t1_inferred_i_2/I0
Type 2 : BUFGCTRL.O->SLICEL.CLK
-----Num Open nets: 20
-----Representative Net: Net[43] u_atlanta/u_pwd0_top/tx_fpll[0].u_tx_fpll/fpga_int_pll_on.u_pll/tx_fpll_ckout[0]
-----BUFGCTRL_X0Y29.O -> SLICE_X227Y142.CLK
-----Driver Term: u_atlanta/u_pwd0_top/tx_fpll[0].u_tx_fpll/fpga_int_pll_on.u_pll/clk_buf.u_clk_output0_buf/O Load Term [40569]: u_atlanta/u_pwd0_top/u_pwd0_clock_mon/u_tx0_pxl_clk_mon/clock_count_hold_reg[0]/C
Ending Interactive Router Task | Checksum: d213ae5b

Time (s): cpu = 00:04:27 ; elapsed = 00:01:49 . Memory (MB): peak = 17025.113 ; gain = 90.551 ; free physical = 49105 ; free virtual = 501827
INFO: [Common 17-83] Releasing license: Implementation
10 Infos, 0 Warnings, 1 Critical Warnings and 0 Errors encountered.
route_design failed
route_design: Time (s): cpu = 00:06:47 ; elapsed = 00:03:37 . Memory (MB): peak = 17025.113 ; gain = 114.254 ; free physical = 49105 ; free virtual = 501827

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Voyager
Voyager
1,194 Views
Registered: ‎10-12-2016

Re: net routable but not routed ?

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@drjohnsmith,

Yes, I am using xc2000T and vivado 2017.4.1 version.

 

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Moderator
Moderator
1,178 Views
Registered: ‎03-16-2017

Re: net routable but not routed ?

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Hi @ssampath,

Are you using BUFG in OOC module? If yes, please check this forum threads- https://forums.xilinx.com/t5/Design-Methodologies-and/BUFG-in-OOC-module-cannot-be-routed-from/m-p/818884/highlight/true#M4588

And if possible use latest Vivado tool - version 2018.3. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Scholar drjohnsmith
Scholar
1,167 Views
Registered: ‎07-09-2009

Re: net routable but not routed ?

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I think your not, the xc2000T went EOL about 20 years ago.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Xilinx Employee
Xilinx Employee
1,160 Views
Registered: ‎05-08-2012

Re: net routable but not routed ?

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Hi @ssampath.

Is the full failing implementation log file available? It looks like the BUFG is driving a non-clock pin for one of the failures. This is legal, but when a BUFG drives a large number of non-clock pins, the routing can be difficult. I would expect messaging to indicate so.


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Voyager
Voyager
1,145 Views
Registered: ‎10-12-2016

Re: net routable but not routed ?

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Voyager
Voyager
1,132 Views
Registered: ‎10-12-2016

Re: net routable but not routed ?

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Hi , 

 

I tried 2018.2 version also still same issue. 

1) Strategy: Congestin_SSI_spread_LOgic_high 

        status: One net is routable but not routed, 

2) For all other strategies:

  status:  many number of nets are not routed. 

Actually device having lot of space am using not more than 50% also. 

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Xilinx Employee
Xilinx Employee
1,113 Views
Registered: ‎05-08-2012

Re: net routable but not routed ?

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HI @ssampath.

Thanks for attaching the log. Below are the messages I was looking for. This is indicating trouble with the global clock routing to specific SLICEs. Since there can be no more than 2 non-clock pin connections to a global clock within a SITE, I would check the SLICE from the message, and reduce the number of clocks driving this site is 2 or less. You might need to constrain certain elements LUT/FFs to be in separate SITEs.

}
Phase 3.7 Small Shape Detail Placement
WARNING: [Constraints 18-647] Placement may not be routable. The following cell(s) are grouped together and are placed in one single tile. The total number of clocks on non-clock pins of these cells is greater than 2, therefore, placer is not able to legalize the design to satisfy the suggested number of clocks that can drive non-clock pins in a single tile. Please modify the design such that each cell has at most 2 clocks driving its non-clock pins. Also, if one or more cells should be grouped together and placed in one tile, make sure the total number of such clocks does not exceed the maximum suggested.
u_atlanta/u_pwd0_top/u_pwd0_reg/u_pwd0_reg_blk/simg_cell_clk_buf.buffer_H_i_2

WARNING: [Constraints 18-643] Placement may not be routable as design contains luts and/or flops whose data pins are driven by global clock signals and final placement is such that the number of such signals exceed the suggested number of such clocks in a single tile, which is 2. The following clock nets need to be routed to non-clock pins in tile CLBLL_L_X144Y49:
u_atlanta/u_pwd0_top/u_pwd0_clk_gen/u_atlanta_pwd_clk_gen/u_clk_1x_rxCT[0]/rstSnc1_n_reg[0], fpga_rx0_clk18, and clk_25mhz
WARNING: [Constraints 18-647] Placement may not be routable. The following cell(s) are grouped together and are placed in one single tile. The total number of clocks on non-clock pins of these cells is greater than 2, therefore, placer is not able to legalize the design to satisfy the suggested number of clocks that can drive non-clock pins in a single tile. Please modify the design such that each cell has at most 2 clocks driving its non-clock pins. Also, if one or more cells should be grouped together and placed in one tile, make sure the total number of such clocks does not exceed the maximum suggested.
u_atlanta/u_pwd0_top/u_pwd0_reg/u_pwd0_reg_blk/clk_inferred_i_2__3

WARNING: [Constraints 18-643] Placement may not be routable as design contains luts and/or flops whose data pins are driven by global clock signals and final placement is such that the number of such signals exceed the suggested number of such clocks in a single tile, which is 2. The following clock nets need to be routed to non-clock pins in tile CLBLM_R_X157Y49:
u_atlanta/u_pwd0_top/u_pwd0_clk_gen/u_atlanta_pwd_clk_gen/u_clk_1x_rxCT[0]/rstSnc1_n_reg[0], u_atlanta/u_pwd0_top/sherman_pwd_wrap[0].u_sherman_pwd_wrap/u_sherman_pxl_pll/fpga_int_pll_on.u_pll/CLK, fpga_rx0_clk18, and clk_25mhz


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Voyager
Voyager
1,098 Views
Registered: ‎10-12-2016

Re: net routable but not routed ?

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Hi @marcb

 

Thank You so much, can you suggest any solution for this. 

Is it okay if i connect BUFG->{BUFH0, BUFH1} and these BUFH's will route to local logic in that region ?

 

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Xilinx Employee
Xilinx Employee
1,082 Views
Registered: ‎05-08-2012

Re: net routable but not routed ?

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Hi @ssampath.

The issue is that there are more than 2 loads within a single SLICE that are driven by global clocks, but are non-clock pins. I would take a look at the SLICE from the log message that correlates to the failing clock net. Are the elements constrained to the same SLICE in any way? They would need to be in separate SLICE sites to avoid the routing error.


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Historian
Historian
1,071 Views
Registered: ‎01-23-2009

Re: net routable but not routed ?

Jump to solution

To be a bit clearer...

Yes, there are physical limitations as to how many clock signals (signals on clock nets) can be used as data pins of CLBs. The reason that this limitation is generally not a problem is that you should not be using clocks as data.

A clock should only be used to clock clockable cells - they should go directly to the C port of flip-flops in the slice, the IOB flip-flops, the ISERDES/OSERDES. the block RAMs, the DSPs, the distributed RAMs, but not to the D (or CE) pin of flip-flops or the data pins of LUTs or RAMs or anything else. With a small number of exceptions, doing this is usually "bad design".

So you need to look at your source and figure out how/why you are using a clock as a data signal and fix the RTL code to not do that...

Avrum

Voyager
Voyager
1,060 Views
Registered: ‎10-12-2016

Re: net routable but not routed ?

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Hi @marcb,  @avrumw@hemangd

 

There are no constraints on that but code is like this. 

module fpga_buff_lut_keep #(
parameter width = 2
)
(
output [width-1:0] out,
input [width-1:0] in
);

(* dont_touch = "true" *) wire [width-1:0] t1;
(* dont_touch = "true" *) wire [width-1:0] t2;

assign t1 = ~in;
assign t2 = ~t1;
assign out = t2;

endmodule

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Xilinx Employee
Xilinx Employee
965 Views
Registered: ‎05-08-2012

Re: net routable but not routed ?

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Hi @ssampath.

Is this net a high fanout net? If not, are you adding the BUFG to the path? If the post-opt_design DCP is able to be attached, this might help to isolate the issue.

 

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Voyager
Voyager
902 Views
Registered: ‎10-12-2016

Re: net routable but not routed ?

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HI @marcb

Thank You all. 

I modified the RTL code and  resolved the issue. 

Thank You

S Sampath

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