10-11-2018 02:25 AM
I have finished a project using ISE 14.7, and it works well on a FPGA board. But in my ISE project, I can not check any detailed reports, such as synthesis report, power report. Is there any option setting to solve this problem?
implement design successfully
but no reports generated
10-11-2018 02:36 AM - edited 10-11-2018 02:38 AM
I am not sure why the Detailed Report section is coming as grey out but the reports will still be available. You can open the reports using a text editor:
*.syr - synthesis report (XST)
*.bld - translation (ngdbuild) report
*.mrp - map report
*.par - place & route report
*.twr - Poset P&R timing report, text
*.bgn - BitGen report
Check this AR# link, might be the reason for grey out:
10-11-2018 02:39 AM
Below link gives the possible cause of the reports been greyed out in the Design summary view. Have a look.