opt_design Resynthesis: segmentation fault

[michi.b]

Hi,

I have a question about the latest Xilinx Vivado Version 2017.4 on SuSe Enterprise 11.4 64-bit (with Intel Xeon)

During implementation steps I recognized a message in step resynthesis of "opt_design -directive ExploreSequentialArea" (using max. 16 threads):

Phase 8 Resynthesis
/nfs/lz/share/SBRi3_Devel_Soft/Xilinx/vivado_2017.4/Vivado/2017.4/bin/loader: line 194:  8229 Segmentation fault      "$RDI_PROG" "$@"
/nfs/lz/share/SBRi3_Devel_Soft/Xilinx/vivado_2017.4/Vivado/2017.4/bin/loader: line 194:  8210 Segmentation fault      "$RDI_PROG" "$@"
/nfs/lz/share/SBRi3_Devel_Soft/Xilinx/vivado_2017.4/Vivado/2017.4/bin/loader: line 194:  8273 Segmentation fault      "$RDI_PROG" "$@"
/nfs/lz/share/SBRi3_Devel_Soft/Xilinx/vivado_2017.4/Vivado/2017.4/bin/loader: line 194:  8306 Segmentation fault      "$RDI_PROG" "$@"
/nfs/lz/share/SBRi3_Devel_Soft/Xilinx/vivado_2017.4/Vivado/2017.4/bin/loader: line 194:  8378 Segmentation fault      "$RDI_PROG" "$@"
/nfs/lz/share/SBRi3_Devel_Soft/Xilinx/vivado_2017.4/Vivado/2017.4/bin/loader: line 194:  8435 Segmentation fault      "$RDI_PROG" "$@"
/nfs/lz/share/SBRi3_Devel_Soft/Xilinx/vivado_2017.4/Vivado/2017.4/bin/loader: line 194:  8468 Segmentation fault      "$RDI_PROG" "$@"

I already started Vivado with: "vivado -stack 20000 *.xpr " but the problem still comes up.

The implementation is still running but I don't know if it will come to an end..

My normal synthesis was fine and I didn't see this message.

I tried with my Windows 7 64-bit, too, and I did not receive this message (only 8 threads).

When I run opt_design resynthesis with just 1 thread it will finalize...after 1h and 40minutes.

The design is used for a Virtex-7 FPGA and it's really big..up to 90% of FPGA resources are used after placement step.

Do you have any idea if this is an error or just a notification?

Is there any impact on my design results(optimizations, better resynth, etc)? 

Is there a problem to run this step multi-threaded? Because it takes really long!

Best regards

Michael

[syedz]

@michi.b,

Try using different directives for opt_design (Explore) 

The error is an internal crash which should not happen. Can you please share synth dcp to get it fixed in vivado tool. 

--Syed

[michi.b]

@syedz,

Thanks for your quick answer! I tried running "opt_design -directive Explore".

The seg. fault didn't come up with this directive, but Vivado didn't start resynthesis, too.

I don't know, how important this step is, but I think a resynthesis with the timing constraints could be useful..

Sharing the design checkpoint is not possible currently. I'll try to extract some blocks which I can not share.

After that I'll try to reproduce the problem without the block. If the message will come up again I'll let you know and share the design checkpoint without the secret implementation.

Best regards

Michael

[syedz]

@michi.b

resynthesis will try to reduce the combinational and sequential logic. 

If you can share the dcp or design then it will be very much helpful

--Syed

[michi.b]

@syedz

I've uploaded the synthesized dcp to the ezmove link you've sent to me via mail.

If you need any further information about the design to fix this, please let me know!

Kind regards,

Michael

[syedz · Accepted solution]

@michi.b,

Please move forward with design by using Explore directive for opt_design. The issue will be fixed in the future release of Vivado.

--Syed