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Visitor aschweiz
Registered: ‎03-12-2018

opt_design fails with Application Exception


today I made a small change to my design and was unable to complete the implementation run. Implementation was working fine until two or three weeks ago.

Vivado 2018.1 now fails with the following error message:

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
ERROR: [Vivado_Tcl 4-131] Power Optimization encountered an exception: ERROR: [Common 17-70] Application Exception: Power Optimization aborted at r:/wall/workspaces/mwall62/sub/REL/2018.1/src/shared/pwropt/core/cmd_parser.cpp:550

The problem persisted even after I had reverted my change, and even after I had rolled-back everything in the design to a known-good state in the SVN repo.

I suspected that a Windows 10 update might have triggered this issue and reverted the updates from the past few weeks. Unfortunately, that didn't help.

I then upgraded to Vivado 2018.3 and tried again, but got exactly the same error.

What helped was to add these options to the opt_power step (which I found in another thread):

-verbose -retarget -propconst -sweep

I'm using a MicroBlaze MCS core (v3.0 rev8) in this design.

The operating system is Win 10 Pro, V 1809 build 17763.1, 64-bit x64, 32 GB, i7-8700K

Does anybody have an idea what could be causing this problem and how to fix it?



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Xilinx Employee
Xilinx Employee
Registered: ‎05-08-2012

Re: opt_design fails with Application Exception

Hi @aschweiz.

The failure looks to be within the -bram_power_opt phase of opt_desgin. This is not expected behavior, and should be reported. Is the design available to attach? If not, is the Block Diagram portion of the design available (write_bd)?

Don’t forget to reply, kudo, and accept as solution.

Don’t forget to reply, kudo, and accept as solution.
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