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pipeline concept in Xilinx

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Visitor
Posts: 6
Registered: ‎08-03-2016
Accepted Solution

pipeline concept in Xilinx

Hi. I am a university student and a novice in VHDL. I have done some very simple assignments using VHDL and a question about pipeline came up to me.

 

I was told from the text books that pipeline can be used to increase the output rate of process. So I think it is preferred to pipeline whenever I can. But when do I actually need to pipeline?

 

I wrote a little test code of an arithmetic p1*p2+p3*p4. Theory wise I should split this operation to parts and pipeline them.

How ever if I just write the equation without partitioning I still observe pipelined results from ISIM.

 

So my question is when is it necessary to purposely pipeline?

 

Sorry for this very general question but all answers are welcomed.

 

My code is below if there is any suggestions about my coding style please don't hesitate to point out.

 

Many Thanks

 

Sinerely

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;


entity sfadf is
     port(a,b,c,d : in std_logic_vector(2 downto 0);
            en,clk : in std_logic;
            dout : out std_logic_vector(5 downto 0));
end sfadf;

 

architecture Behavioral of sfadf is
signal p1 : unsigned(2 downto 0) := (others=>'0');
signal p2 : unsigned(2 downto 0):= (others=>'0');
signal p3 : unsigned(2 downto 0):= (others=>'0');
signal p4 : unsigned(2 downto 0):= (others=>'0');
signal psum : unsigned(5 downto 0):= (others=>'0');
begin
     arith : process(clk,en)
     begin
          if (en='0') then
               psum <= (others => '0');
          elsif(rising_edge(clk))then
               p1 <= unsigned(a);
               p2 <= unsigned(b);
               p3 <= unsigned(c);
               p4 <= unsigned(d);
               psum <= p1*p2+p3*p4;
          end if;

     end process;
dout <= std_logic_vector(psum);
end Behavioral;

 

garbage.PNG


Accepted Solutions
Highlighted
Teacher
Posts: 5,130
Registered: ‎03-31-2012

Re: pipeline concept in Xilinx

@liuz3 pipelining is most useful when input is available in a streaming fashion and the output is not necessary to make decision on what to do next. In your example it would make sense to have one stage of pipeline to have the multipliers run and another stage for the adder. ie

 

pmul1 <= p1*p2;

pmul2 <= p3*p4;

psum  <= pmul1 + pmul2;

 

The benefit of this schedule is that in the original design, the period of the logic is Tmul + Tadd but in the second one max(Tmul, Tadd) (which is most likely Tmul). So we managed to reduce the period of the design at the expense of some latency. If p1, p2, p3 & p4 are available every cycle, we will get the first output 2 cycles later and then one sum every cycle after that so the overall through will increase (because of the reduced period, ie increased frequency.)

 

PS of course in a "real" design, one would split up the multiplier into stages so that all pipeline stages would be of equal depth and each stage would fit into the desired period perfectly.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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View solution in original post


All Replies
Highlighted
Teacher
Posts: 5,130
Registered: ‎03-31-2012

Re: pipeline concept in Xilinx

@liuz3 pipelining is most useful when input is available in a streaming fashion and the output is not necessary to make decision on what to do next. In your example it would make sense to have one stage of pipeline to have the multipliers run and another stage for the adder. ie

 

pmul1 <= p1*p2;

pmul2 <= p3*p4;

psum  <= pmul1 + pmul2;

 

The benefit of this schedule is that in the original design, the period of the logic is Tmul + Tadd but in the second one max(Tmul, Tadd) (which is most likely Tmul). So we managed to reduce the period of the design at the expense of some latency. If p1, p2, p3 & p4 are available every cycle, we will get the first output 2 cycles later and then one sum every cycle after that so the overall through will increase (because of the reduced period, ie increased frequency.)

 

PS of course in a "real" design, one would split up the multiplier into stages so that all pipeline stages would be of equal depth and each stage would fit into the desired period perfectly.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
Explorer
Posts: 166
Registered: ‎04-12-2017

Re: pipeline concept in Xilinx

[ Edited ]

In your example there isn't a pipeline. The way you wrote it, inside a clocked process, makes the result of the whole operation to be available one clock later. Hence, it is not a pipeline but a sampling of the output of an operation.

 

To make a real pipeline you should have done as muzaffer explained to you.

 

Cheers!

Avi Chami MSc
FPGA Site