place and route problem

[regank33]

I have a current design that I want to keep its exact routing. When I add more circuits to this design, it changes the routing of the original design, even though the new circuitry does not effect the original design. 

when I use UCF constraints to constrain the original design to the updated design, many nets are changed and the design will not map.

How would I go about this problem? 

[austin]

r,

Why do you care?  What problem are you trying to solve?

[bwade]

It sounds like the design coming out of synthesis no longer matches the UCF constraints leading to errors. You can get around this by applying the constraints in the RTL so that the resulting names no longer matter. I could give a more specific answer if you told us what constraints you are using and what errors you are seeing. I would also like to know what problem you are trying to solve with this approach.

[smarell]

If you don't want to disturb the initial part of the design, why don't you consider partitioning the design. Refer to http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/Hierarchical_Design_Methodology_Guide.pdf for more details.

[regank33]

I'm using a phase detector with state machine with a 65ps windows that needs dedicated routing

[regank33]

bwade,

that is just what I was looking for.

Thanks

[regank33]

smarell,

This document will be great for bigger projects. 

Thanks