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Visitor
Visitor
8,272 Views
Registered: ‎12-25-2013

place and route problem

I have a current design that I want to keep its exact routing. When I add more circuits to this design, it changes the routing of the original design, even though the new circuitry does not effect the original design. 

 

when I use UCF constraints to constrain the original design to the updated design, many nets are changed and the design will not map.

 

How would I go about this problem? 

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6 Replies
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Scholar
Scholar
8,270 Views
Registered: ‎02-27-2008

Re: place and route problem

r,

 

Why do you care?  What problem are you trying to solve?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
8,259 Views
Registered: ‎07-01-2008

Re: place and route problem

It sounds like the design coming out of synthesis no longer matches the UCF constraints leading to errors. You can get around this by applying the constraints in the RTL so that the resulting names no longer matter. I could give a more specific answer if you told us what constraints you are using and what errors you are seeing. I would also like to know what problem you are trying to solve with this approach.

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Community Manager
Community Manager
8,246 Views
Registered: ‎07-23-2012

Re: place and route problem

If you don't want to disturb the initial part of the design, why don't you consider partitioning the design. Refer to http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/Hierarchical_Design_Methodology_Guide.pdf for more details.

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Visitor
Visitor
8,199 Views
Registered: ‎12-25-2013

Re: place and route problem

I'm using a phase detector with state machine with a 65ps windows that needs dedicated routing

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Visitor
Visitor
8,197 Views
Registered: ‎12-25-2013

Re: place and route problem

bwade,

 

that is just what I was looking for.

 

Thanks

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Visitor
Visitor
8,196 Views
Registered: ‎12-25-2013

Re: place and route problem

smarell,

 

This document will be great for bigger projects. 

 

Thanks

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