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Voyager
Voyager
684 Views
Registered: ‎10-12-2016

placement error even clock from IOB to PLL of same region ?

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HI Friends,

placement error even clock from IOB to PLL of same region ?

 

iob_pll_backbone.png

For any help or suggestions are highly appreciated.

Thank You

S Sampath

-Sampath
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1 Solution

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Moderator
Moderator
641 Views
Registered: ‎05-08-2012

Hi @ssampath.

The CLOCK_DEDICATED_ROUTE constraint can be set as indicated in the error, but this is not recommended.


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Moderator
Moderator
675 Views
Registered: ‎01-16-2013

@ssampath

 

The site IOB_X0Y141 for xc7k410tffg676-2 is not clock capable IO hence you are receiving the error. If you chage the port to clock capable IO (SRCC or MRCC) then you will not see the error message.

Capture.JPG

 

Check 7 series clocking resource user guide for more details:

https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf#page=24

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Voyager
Voyager
656 Views
Registered: ‎10-12-2016

HI @syedz

 

Thank You, but we are connecting this board to external. Now i don't have any option, Is there any fix for this ?

-Sampath
0 Kudos
Highlighted
Moderator
Moderator
642 Views
Registered: ‎05-08-2012

Hi @ssampath.

The CLOCK_DEDICATED_ROUTE constraint can be set as indicated in the error, but this is not recommended.


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------

View solution in original post