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Visitor
Visitor
4,732 Views
Registered: ‎12-09-2010

problem of implement

my project include two modules. output of part1 will transfer to part2. there are not feed-back.

the one bitfile is generated by part1 module , a another is generated by  the whole project .

in FPGA testing, the output of part1 are different between the two bitfiles. 

tools are synplify pro 9.6.1 and ise12.1. LUT useage are 70% and 18%. FPGA is Virtex 5

 

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awillen
Mentor
Mentor
4,731 Views
Registered: ‎11-29-2007

So, what do you want us to do about it?



Please google your question before asking it.
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Visitor
Visitor
4,728 Views
Registered: ‎12-09-2010

sorry! why are there different result?

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eteam00
Instructor
Instructor
4,723 Views
Registered: ‎07-21-2009

sorry! why are there different result?

Is there any particular reason they should be the same?  You haven't mentioned any reasons, so far.

 

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