12-13-2010 11:15 PM
my project include two modules. output of part1 will transfer to part2. there are not feed-back.
the one bitfile is generated by part1 module , a another is generated by the whole project .
in FPGA testing, the output of part1 are different between the two bitfiles.
tools are synplify pro 9.6.1 and ise12.1. LUT useage are 70% and 18%. FPGA is Virtex 5
12-13-2010 11:20 PM
So, what do you want us to do about it?
12-13-2010 11:39 PM - edited 12-17-2010 12:12 AM
sorry! why are there different result?
Is there any particular reason they should be the same? You haven't mentioned any reasons, so far.
- Bob Elkind