problem of implement

adsad · ‎12-13-2010

my project include two modules. output of part1 will transfer to part2. there are not feed-back.

the one bitfile is generated by part1 module , a another is generated by the whole project .

in FPGA testing, the output of part1 are different between the two bitfiles.

tools are synplify pro 9.6.1 and ise12.1. LUT useage are 70% and 18%. FPGA is Virtex 5

awillen · ‎12-13-2010

So, what do you want us to do about it?

Please google your question before asking it.
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adsad · ‎12-13-2010

sorry! why are there different result?

eteam00 · ‎12-13-2010

sorry! why are there different result?

Is there any particular reason they should be the same? You haven't mentioned any reasons, so far.

- Bob Elkind

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