problem with dcm clock output driving mux selector

[bontorhumala]

Hello my name is Bontor. I am trying to implement my HDL design (fft module) in Digilent Atlys board that use Spartan 6 as FPGA core. Thee board supply 100 MHz clock while my design can only run at 18 MHz. So I use DCM coregen module to reduce the clock to 18 MHz.

Problem is, DCM output is from a BUFG, and in my design, the clock signal is used to drive some mux, as selector input. When I straightforwardly connect DCM clock output to the mux selector input, I get the ERROR:Place:1206, saying" the global buffer instance, driving the net, that is driving the following (first 30) non-clock source pins off chip."

After reading on this forum, I found similar problem in:

http://www.xilinx.com/support/answers/35032.htm

The solution is to use ODDR2 instantiation (clock forwarding technique), where the clock signal does not drive the load pin directly, instead act as input to ODDR2, then the output of ODDR2 is used to drive the pin. 

I tried to implement this in my design, but it failed,, saying "ERROR:Pack:2530 - The dual data rate register failed to join an OLOGIC component as required.". Which is clear because I used the ODDR2 output to drive internal signal instead of an output pin (I realize ODDR2 output must drive output pin from http://forums.xilinx.com/t5/Virtex-Family-FPGAs/problem-with-ODDR-bloc/td-p/105919) 

So, I need a solution on how to use output of DCM module to drive internal pin (in this case, mux input). Is there similar module like ODDR2, but the output can be used in internal signal?

I have been trying to solve this in the last 7 hours, please help me. Any help would be greatly appreciated.

[eteam00]

Using an 18MHz clock to generate 36MHz timed logic is awkward. Generating 36MHz signals for internal use in a system clocked at 18MHz does not make sense.  Why would you do that?

Using a 36MHz clock for 36MHz logic is the clean solution.

You can implement simple logic running at 36MHz clock.  The logic would alternate selecting between two inputs, which is (effectively) time multiplexing at 36MHz rate.  This is equivalent to using a 18MHz clock to multiplex on alternate phases of the clock.

example:

always @(posedge Clock36M)

  begin

    mux_select <= ~mux_select;  // toggle flip-flop

    mux_out  <=  mux_select ? mux_input_A : mux_input_B;  // time multiplex inputs A and B

  end

-- Bob Elkind

[bontorhumala]

Thanks for your reply Bob. I do it because i use folding technique in my design and I want different use of a bfu core at positive edge and negative edge. I will look to my design to change implementation of the folding technique, maybe using a counter is a good solution?

On the other hand, do you have idea on how to reduce clock frequency without using DCM or other resource that use BUFG as buffer? Thanks in advance

[eteam00]

I do it because i use folding technique in my design...

I am unfamiliar with the term "folding technique".  Do you mind clarifying the term?

... and I want different use of a bfu core at positive edge and negative edge.

If I understand you correctly, you have two similar logic blocks operating on opposite phases of a single system clock.  Is this correct?

If this is correct, are the blocks running at 18MHz or 36MHz?  Or some other frequency?

Perhaps if you described your system clocks (*all* of them) and how they are used, it would be easier to provide a useful suggestion or two.

On the other hand, do you have idea on how to reduce clock frequency without using DCM or other resource that use BUFG as buffer?

If the lower clock frequency is related to the source clock frequency by some nice (preferably even) integer, the matter of clock division is simple enough.  Otherwise, a PLL or DCM solves the problem by applying both multiplication and division.

As for avoiding BUFG, this is a dangerous (risky) endeavour.  Clocked digital logic systems require tight clock skew control.  Too much clock skew is fatal, regardless of operating frequency.  BUFG is the primary means of both buffering and distributing clocks to the entire fabric with (essentially) zero skew.  In other words, BUFG is your friend.

It sounds like you are doing your best to reduce device power consumption.  Is this a correct assessment?

-- Bob Elkind

[bontorhumala]

Thank you for your response.

I do it because i use folding technique in my design...

I am unfamiliar with the term "folding technique".  Do you mind clarifying the term?

I use the term "folding" to refer to hardware sharing. 

... and I want different use of a bfu core at positive edge and negative edge.

If I understand you correctly, you have two similar logic blocks operating on opposite phases of a single system clock.  Is this correct?

Yes.  At positive edge, i need the bfu (the shared hardware) to run for the 'x' function, and on the neg edge, i needit to run for the 'y' function

If this is correct, are the blocks running at 18MHz or 36MHz?  Or some other frequency?

Yeah, it basically running at 36 MHz

Perhaps if you described your system clocks (*all* of them) and how they are used, it would be easier to provide a useful suggestion or two.

Basically I just use 1 system clock, and this "half clock" approach is only used in this particular hardware I justmentioned above.

As a solution, I am thinking of using 2 clock. 1 clock is for general system, and the other, clocked at twice the general clock, is used to run a 1 bit counter (counter replace half clock approach).  When this counter is 0, I use the shared hardware to work for x function, then when it is 1, used for y function. What do you think of this double clock approach? I am planning to use DCM to generate both clock

[eteam00]

Have you considered implementing a single hardware block clocked at 36MHz, alternating between 'X' and 'Y' threads on consecutive cycles?  Not only does this simplify timing analysis, but it reduces the aggregate datapath size by roughly half.

Even if you implement two parallel datapaths operating concurrently, both datapaths should be operating on the same clock edge.

What you cannot do is clock a single datapath on both positive and negative clock edges.  There is no hardware construct in a Xilinx FPGA which can be clocked on more than a single clock edge.  Your options are limited to two parallel datapaths clocked at frequency "F" or a single multi-thread datapath clocked at frequency "2F".

This sounds like a school project or thesis.

-- Bob Elkind

[bontorhumala]

Have you considered implementing a single hardware block clocked at 36MHz, alternating between 'X' and 'Y' threads on consecutive cycles?  Not only does this simplify timing analysis, but it reduces the aggregate datapath size by roughly half.

Yes, I think I am going to look to that approach. Thank you for your idea. This is actually a school project and going to be proposed to compete in a LSI competition.

[kanwal_]

please tell me how to instantiate ODDR block 2 remove error 1203? urgently plz give me the ans ........

[kanwal_]

hi

please tell me how to instantiate ODDR block to remov DCM clocking error 1203 in spartan 6......plz urgently give me the ans?

[kanwal_]

hi

please tell me how to instantiate ODDR block to remov DCM clocking error 1203 in spartan 6......plz urgently give me the ans?

[eteam00]

Kanwal,

1.  Please do not open a new problem or question in an existing thread.  One problem or topic per thread, please.  Instead, you should open a new thread (which you have already done).

2.  Please, one post or one thread is sufficient.  You have created 4 posts in these forums with the same request.  This clutters the forums, makes it difficult to see all responses, and adds confusion.  The thread you already created is entirely sufficient.

3.  This is a user-to-user forum which is supported by volounteers.  You should not expect immediate responses.  Be patient.

4.  Please read the New Users README, which includes both forums use guidelines and some useful information links.

-- Bob Elkind