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Explorer
Explorer
3,793 Views
Registered: ‎12-22-2010

reduce frequency and insert to DCM

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dear memeber

i try to implement this  simple system

 

eee.png


i will take clk0 and clk90 as output

 

this problem appear

ERROR:NgdBuild:770 - IBUFG 'FSDDF/CLKIN_IBUFG_INST' and BUFG 'BUFG_inst' on net
   'CLK2' are lined up in series. Buffers of the same direction cannot be placed
   in series.
ERROR:NgdBuild:924 - input pad net 'CLK2' is driving non-buffer primitives:

i try to add inout buffer  and input clock buffer and follow the method here  http://www.xilinx.com/support/answers/34771.htm


same thing

please any help

my code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
Library UNISIM;   --for including the Language template "BUFG"
use UNISIM.vcomponents.all;
--------------------------------------------

entity test is
port (clk : in std_logic;     --input clock
      a2,a90 : out std_logic  --output signal which changes with "clk" signal
     );
end test;

architecture Behavioral of test is
---------------------------------------------------------------------
signal CLK2,temporal  : std_logic:='0';
signal counter : STD_LOGIC_vector(8 downto 0):="000000000";  
---------------------------------------------------------------------
COMPONENT DCC
 PORT(    CLKIN_IN       : in    std_logic; 
          RST_IN          : in    std_logic; 
          CLKIN_IBUFG_OUT : out   std_logic; 
          CLK0_OUT        : out   std_logic; 
          CLK90_OUT       : out   std_logic; 
          LOCKED_OUT      : out   std_logic);
END COMPONENT;
begin
--------------------------REDUCE FREQU----------------------------------
    process (clk)
    begin
    if rising_edge(clk) then
    if (counter = "000110001") then  --49
    temporal <= NOT(temporal);
    counter  <= "000000000";
    elsif (counter = "000011000") then --24 half
    temporal <= NOT(temporal);
    counter <= counter + "000000001";
    else
    counter <= counter +"000000001";
    end if;
    end if;
    end process;
------------------------------INSERT TO DCM---------------------------------	 
	  BUFG_inst : BUFG
   port map (
      O => CLK2,     -- Clock buffer output
      I => temporal  -- Clock buffer input
   );
-----------------------------------------------------------------------------
FSDDF:DCC PORT MAP(CLKIN_IN=>CLK2,RST_IN=>'0',CLKIN_IBUFG_OUT=>OPEN,CLK0_OUT=>A2,CLK90_OUT=>A90,LOCKED_OUT=>OPEN);
-----------------------------------------------------------------------------
end Behavioral;

 

 

---------------------------------------------------------------------------------------------
I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
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1 Solution

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Xilinx Employee
Xilinx Employee
4,728 Views
Registered: ‎07-16-2008

Re: reduce frequency and insert to DCM

Jump to solution

The problem here is that in the DCM component, an IBUFG instance already exists. At the top level, DCM's CLKIN is mapped to CLK2, which is output from BUFG. This causes conflict since IBUFG can only be sourced from clock input pad.

 

To resolve the issue, you need to define the clock source as "No Buffer" in DCM clocking wizard and re-generate it.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
4 Replies
Observer vjose
Observer
3,744 Views
Registered: ‎08-01-2012

Re: reduce frequency and insert to DCM

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Hi ,

 

Thanks for the detailed block diagram .

 

1) Can you send me the input frequency of the DCM and output you want to generate

 

Solution

-----------

While generating the DCM can you uncheck the input output buffers . By default this is checked, this means that the buffers are implemented . if this clock is connected to any output buffers this following error would appear. Do try this and let me know.

 

With regards

Vintu

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Explorer
Explorer
3,698 Views
Registered: ‎12-22-2010

Re: reduce frequency and insert to DCM

Jump to solution
THE INPUT FREQUENCY 50MHZ and output 5MHZe
please where can i make a change in my
code to solve the problem as ???
---------------------------------------------------------------------------------------------
I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
4,729 Views
Registered: ‎07-16-2008

Re: reduce frequency and insert to DCM

Jump to solution

The problem here is that in the DCM component, an IBUFG instance already exists. At the top level, DCM's CLKIN is mapped to CLK2, which is output from BUFG. This causes conflict since IBUFG can only be sourced from clock input pad.

 

To resolve the issue, you need to define the clock source as "No Buffer" in DCM clocking wizard and re-generate it.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Explorer
Explorer
3,684 Views
Registered: ‎12-22-2010

Re: reduce frequency and insert to DCM

Jump to solution
thank
---------------------------------------------------------------------------------------------
I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
0 Kudos