04-10-2021 11:02 PM
vivado version:2019.2, device :xcvu440
there are 8-bit width register, they are all triggered by posedge in rtl code. in dcp schematic, they are all triggered by posdge clock. the MSB bit was maped into IOB and others were mapped to slice. it seemed all right.
But when we view the waveform, the MSB bit changes after negedge clock, and the others change after posedge clock. so the logic function is wrong.
why did that happene? Was there a bug in bit generation?
the clock is tck, the wrong bit is instruction, other bits(instruction[6:0] are right. please see the attached code, schematic and wave files.
04-11-2021 11:07 AM
When you say "view the waveform"
is that in the simulator ? if not use the simulator,
if it as in the simulator
you can follow the signals back to see why the output changes as it does.
Do not synthesise / use an ILA until the simulation works,
Regarding IOB registers,
The only real way of forcing use of an IOB register, is to instantiate the native block, probably the DDR.
I know there are other ways, but this always work,
The reason your registers are not in IOB, is either
the tools met your constraints and function without needing to use an IOB.
the optimised code has features that stop it being fitted into an IOB .
04-11-2021 07:39 PM
"view the waveform" means I download the bit into vu440 fpga and catch the wave using protocompiler runtime tools (like chipscope). It is not a simulation and the simulation is all right.
As you see the attached file, the instruction is really mapped into IOB. and the block function is wrong.
I have an other try, moving the instruction from IOB to slice, and then the function is all right. So I am wondering why this happened?
04-12-2021 01:31 AM
If your using the Xilinx ILA to monitor a IOB output,
I think there should be, but check is there a route from the IOB pin back to the ILA in the fpga in the configuration your using,
Is the signal correct on the FPAG pin when you use a scope ?
then we can deduce is it the ILA / connection or the signal,
Did you post PAR simulate to double check ?
04-12-2021 08:05 PM
One thing is that there are only one different synthesis attribute "syn_useioff = 0 or 1" between the two designs. One is OK and the other is wrong.
We do not run the post simulation, we will do it to double check it.
How can I check the route between ILA and IOB?
04-13-2021 01:58 AM
syn_useioff , implies your using Synplify Pro, not the xilinx tools for elaboration,
That's a complete new level of things, thats outside Xilinx control.
strongly suggest that you simulate the post P&R design, to check.
that way we can localise is it the symplify pro / synthesis that is causing you problems, or the P&R or ILA that are causing you problems,