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Visitor bj8201.kim
Visitor
225 Views
Registered: ‎07-11-2019

reset _run sub-module and fail to implementation

I received FPGA project (using vivado 2017.4) build successfully before.

No problem when just reset_run synth_1, reset_run impl_1.

But the problem is occured sub-modules reset like below.

   foreach run [ get_runs ] {
       reset_run [ get_runs $run ]
   }

what do I check first?

Thanks in advance.

 

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3 Replies
Xilinx Employee
Xilinx Employee
208 Views
Registered: ‎05-22-2018

Re: reset _run sub-module and fail to implementation

Hi @bj8201.kim ,

I guess you are trying to reset run for OOC module, if yes then please check below:

You can ashieve that by 

reset_runs <module_name>_synth_1.

For example:

reset_runCapture.JPG

For above any sub module run:

reset_runs MystGthSerdesFreqCounter_KU15P_synth_1

Thanks,

raj

 

 

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Visitor bj8201.kim
Visitor
154 Views
Registered: ‎07-11-2019

Re: reset _run sub-module and fail to implementation

Thanks raj.

C2C_slave_dfpga_v01 -> Regenarate Output Product -> Fail to Launch Run impl1.

What do I do next step?

Plz advice to me.

 

 

Fail to launch run impl_1.jpg
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Xilinx Employee
Xilinx Employee
120 Views
Registered: ‎01-30-2019

Re: reset _run sub-module and fail to implementation

Hi @bj8201.kim ,

I used your TCL commands to reset runs and I was able to reset the runs successfully.

can you check if the TCL console returns the name of the submodule runs when you run get_runs

If not then can you check if the IPs ( for which you are trying to reset the submodule runs ) are locked or not?

If the IP's are locked, then you need to unlock these IP's and then try resetting the run.

 

--Suraj

 

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