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Visitor
Visitor
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Registered: ‎08-16-2020

reuse parameterised verilog modules in vivado design suite

Hi all,

I am trying to reuse the same module with different parameters passing in Verilog vivado, but not able to achieve. I am trying to reuse module1 at different times. Is there any possibility to reuse module with different parameters. Please assist me with this.

module1 #(25) DUT1(...);
module1 #(35) DUT2(...);

 

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Xilinx Employee
Xilinx Employee
184 Views
Registered: ‎01-30-2019

Hi @sl_madh 

More information is required; for us to help you.

Can you elaborate more on from where have you obtained module1? is the module1 a tool generated netlist?

and when do you want to reuse it? In Synthesis or in Implementation? 

 

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