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route_design takes forever Zedboard Vivado17.3

Posts: 1
Registered: ‎01-09-2018

route_design takes forever Zedboard Vivado17.3


I am running the implementation of a vivado 2017.3.1 project for the Zedboard. Unfortunately the implementation is taking forever. Nearly the same project was able to create a bitstream with vivado 2016.3 on another machine. I checked the implementation settings.

How can I find the reason for the problem. There is no error message... and it is running for more than a day.

The log file is attached, I am using Windows 7 and Vivado v2017.3.1 (64-bit).

Thanks in advance,
best regards

Posts: 482
Registered: ‎08-07-2014

Re: route_design takes forever Zedboard Vivado17.3

[ Edited ]

Hi @georgjanisch,


First of there are signification changes b/w 2016.x and 2017.x Vivado versions.


A very likely cause of such a behavior is improper constraining of the design.

I also see a huge huge WNS in your log. In turn the Xilinx router-algo engine is really really trying hard to get a pass. So you might want to re-think on your constraints.


With the infos you have provided, this is all I have to say.

FPGA enthusiast!
Xilinx Employee
Posts: 12
Registered: ‎05-08-2012

Re: route_design takes forever Zedboard Vivado17.3

Hi @georgjanisch


I would try looking at the post-placement netlist (DCP). There is a severe timing failure that would account for the route_design run time. Below is from the given log. Is the full path report available for the WNS path at this stage? The constraints would likely need to be modified.


INFO: [Place 30-746] Post Placement Timing Summary WNS=-78.947. For the most accurate timing information please run report_timing.