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Visitor
Visitor
2,595 Views
Registered: ‎01-09-2018

route_design takes forever Zedboard Vivado17.3

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Hello,

I am running the implementation of a vivado 2017.3.1 project for the Zedboard. Unfortunately the implementation is taking forever. Nearly the same project was able to create a bitstream with vivado 2016.3 on another machine. I checked the implementation settings.

How can I find the reason for the problem. There is no error message... and it is running for more than a day.

The log file is attached, I am using Windows 7 and Vivado v2017.3.1 (64-bit).

Thanks in advance,
best regards
Georg

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Visitor
Visitor
2,901 Views
Registered: ‎01-09-2018

Hello again,
I changed now the timing constraints, however I was not able to reduce this worse negative slack.

When I activated the -verbose option in the implementation settings the implementation suddenly worked.

So thank you for your help!
Best regards
Georg

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Scholar
Scholar
2,581 Views
Registered: ‎08-07-2014

Hi @georgjanisch,

 

First of there are signification changes b/w 2016.x and 2017.x Vivado versions.

 

A very likely cause of such a behavior is improper constraining of the design.

I also see a huge huge WNS in your log. In turn the Xilinx router-algo engine is really really trying hard to get a pass. So you might want to re-think on your constraints.

 

With the infos you have provided, this is all I have to say.

------------FPGA enthusiast------------
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Moderator
Moderator
2,500 Views
Registered: ‎05-08-2012

Hi @georgjanisch

 

I would try looking at the post-placement netlist (DCP). There is a severe timing failure that would account for the route_design run time. Below is from the given log. Is the full path report available for the WNS path at this stage? The constraints would likely need to be modified.

 

INFO: [Place 30-746] Post Placement Timing Summary WNS=-78.947. For the most accurate timing information please run report_timing.

 

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Visitor
Visitor
2,347 Views
Registered: ‎01-09-2018

Thank you very much for your answers. You are right, there might be some issues with the timing constraints. I found the tutorial UG945 (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug945-vivado-using-constraints-tutorial.pdf) and tried create better timing constraints.

However in my design the Constraints Wizard does not show undefined paths or missing constraints. My project exists of a block design with mostly self defined IPs. There are constraints files in those blocks and I think these constraints files are used.

What is the best way to set constraints if self defined IP blocks are used? I read that the last constraint file in the process order is used. However should I delete constraints files in the IP blocks and just have the actual ones in the source folder of the block design project? Or are the constraints files of the IP blocks ignored anyway when there is one in the block design project.

Is there any tutorial or user guide where I can find answers, I didn't find one yet...

Thanks,
Georg

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Highlighted
Visitor
Visitor
2,902 Views
Registered: ‎01-09-2018

Hello again,
I changed now the timing constraints, however I was not able to reduce this worse negative slack.

When I activated the -verbose option in the implementation settings the implementation suddenly worked.

So thank you for your help!
Best regards
Georg

View solution in original post

0 Kudos