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Scholar pedro_uno
Scholar
23,192 Views
Registered: ‎02-12-2013

set_property IOB

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Hello All,

 

I have decided to force myself to learn Vivado.  Right now I am just making sure that I can do everything that I used to do in ISE. Then I will try the HLS stuff.

 

One thing I always do is force input and output registers into the IOBs.  There was an implementation option in ISE but I cannot find anything similar in Vivado.  Also, UG912 says you can do it with this TCL syntax in your XDC file.

 

set_property IOB TRUE [get_ports {led[0] led[1] led[2] led[3]}]

 

Unfortunately this command causes the following error. led[**] are registered outputs of my test design.

 

ERROR: [Netlist 29-69] Cannot set property 'IOB', because the property does not exist for objects of type 'port'.

 

Can anyone tell me a way to accomplish IOB register packing in Vivado?

 

Thank you,

 

     Pete

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Xilinx Employee
Xilinx Employee
28,353 Views
Registered: ‎09-20-2012

Re: set_property IOB

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Hi,

 

You can use the below commands in vivado 2013.x for setting the IOB property to TRUE on all Input and output ports in the design.

 

set_property IOB TRUE [all_inputs]
set_property IOB TRUE [all_outputs]

 

Thanks,

Deepika.

Thanks,
Deepika.
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26 Replies
Scholar austin
Scholar
23,186 Views
Registered: ‎02-27-2008

Re: set_property IOB

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Pete,

 

Getting used to the new TCL interface does take some effort.  I would experiment with get_property to get all the properties of the things that it is complaining about (led ports).  By doing this, I was able to figure out a lot of what I needed to know.

 

And, if you find something you cannot do in Vivado, please post it (like you did), or even submit a webcase.  Right now is a critical time, where folks are working on bugs, missing components, etc.  Vivado is already great, but it needs to be even better,  And, we need your help to identify those elements that still need to be polished.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
23,178 Views
Registered: ‎07-01-2008

Re: set_property IOB

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IOB properties can only be applied to register cells, not ports.

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Scholar austin
Scholar
23,176 Views
Registered: ‎02-27-2008

Re: set_property IOB

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Bruce,


That is what I suspected. When I first started to use TCL I discovered that objects (cells, ports, etc.) all have their own properties, and only by getting those properties, and looking at them could I start to make sense of what I could set.

 

Thank you for replying here,

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Scholar pedro_uno
Scholar
23,174 Views
Registered: ‎02-12-2013

Re: set_property IOB

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Does anyone actually know how to duplicate the "Pack I/O Registers for inputs and outputs" syntax of ISE?

 

I guess I am looking for a real answer, not "fiddle with it till you are red in the face and maybe you will get lucky".  UG912 specifcally recommends the syntax I used.  Now I have several hours invested, just duplicating one function of ISE.

 

I will file a webcase. There goes another hour.

 

  Pete

 

 

 

 

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Xilinx Employee
Xilinx Employee
23,172 Views
Registered: ‎07-01-2008

Re: set_property IOB

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See my answer in your other thread. That's not the question you asked here.

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Scholar austin
Scholar
23,167 Views
Registered: ‎02-27-2008

Re: set_property IOB

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Pete,

 

I did not say 'fiddle with it until you are red in the face.'  I suggested that you study the properties of the various elements carefully to gain an understanding.

 

If you wish to have a step by step list of features and capabilities when going from ISE to Vivado (how to do), Where would we start?  With perhaps 10,000 designs happening at any given moment in time, how would we know what features are 'important' and what features are 'unimportant?'

 

One goal of Vivado is to make it more useful, by having it make smarter decisions, removing the need to direct specifics (they get directed automatically because its obvious what you are trying to do...).  Given that goal, much of what you may have had to do in the past, should not be required for you to do in the future.  Did the unmodified implementation meet your constraints?  If so, why would you need to do anything more?  This is what is needed by the implenters (for something that used to be possible, but is no longer possible).  In this case, Bruce has replied and shown how it is possible.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Scholar pedro_uno
Scholar
23,155 Views
Registered: ‎02-12-2013

Re: set_property IOB

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I would start by clicking through the short list of options built into the synthesis and implement options of ISE and then make sure there is a well documented way to do those things in Vivado.  Yes, Vivado synthesis does not seem to be smart enough to put IO registers in the IOB just to meet clock-to-out timing.  It missed by a mile and left the registers inside.

 

Here is some wordy and fragile TCL syntax I came up with the work around the problem.  It turns out that Vivado synthesis puts an _reg into the name on the output of the register.

 

set_property IOB TRUE [get_cells -hierarchical led_reg[*]]
set_property IOB TRUE [get_cells -hierarchical enable_reg_reg]

 

Anyway, there is probably a better way but I hope this helps someone else out there.

 

I have submitted a webcase and referenced this thread there.

 

I shouldn't be so critical, only this is about the 5th time I've been through this.  I'm sure Vivado will be great.

 

 

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DSP in hardware and software
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Scholar pedro_uno
Scholar
23,153 Views
Registered: ‎02-12-2013

Re: set_property IOB

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You only said that you did not know how to do it.

You did not tell me how to put I/O registers into the IOB.

Really, if you know how to do just put a TCL code snippet in your answer or something.

There is no reason to be coy. Folk are just trying to get their designs working.


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DSP in hardware and software
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Historian
Historian
23,142 Views
Registered: ‎01-23-2009

Re: set_property IOB

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The IOB property needs to be set on the FF that you want to pack into the IOB. Presumably, the led[*] ports are driven (direcly) from some flip-flops - it is these FFs that you want to set the property on.

 

Finding these FFs can be done using the mechanisms within Vivado to traverse the hierarchy - they can be done with complex relationships using get_cells -of_objects... I find that the easiest way of doing it is with the "all_fanin" command. This command allows you to identify things that are combinatorially reachable by other things. So, to do what you want, you can use the following command (I haven't syntax checked it - but the essence is correct).

 

 

set_property IOB true [all_fanin -only_cells -startpoints_only -flat [get_ports {led[0] led[1] led[2] led[3]}]]

 

[Edit: Since this thread, Xilinx added the capability to add the IOB property to the port. Now you can use

 

set_property IOB true [get_ports led[*]]

 

or even

 

set_property IOB true [all_inputs]

set_property IOB true [all_outputs]

 

]

Avrum

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Observer davidh1901
Observer
21,388 Views
Registered: ‎07-27-2008

Re: set_property IOB

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I just had the same problem.

I'm sorry, but "fiddle with it until you are red in the face" is also what I saw in your previous answer.

The manual explicitly states that the syntax specified in the original post is correct. I quote from UG912 :

 

--------

 

The IOB attribute can be placed on an instantiated or inferred register connected to a
top-level port. Place the register connected to ACK in the input logic site.
XDC Syntax
set_property IOB value [get_ports port_name]
Where
• value is TRUE or FALSE.
Properties Reference Guide www.xilinx.com 46
UG912 (v2012.3) November 16, 2012
IOB
XDC Syntax Example
# Place the register connected to ACK in the input logic site
set_property IOB TRUE [get_ports ACK]
When this property is set in both HDL code and in XDC, the XDC property takes precedence.

 

-------------

 

Perhaps UG912 could be corrected to something more helpful.

 

Constraints generally are really painful to work with. You can only see if something works after you have built the design, which usually takes an hour or more. Digging through the netlist to find elements and then setting constraints that may or may not work can consume weeks of design time.

 

For another example of this sort of problem : The constraints generated by Vivado for a dual clock fifo core result in an warning from the tool, and are then ignored.

 

Also, while Vivado is a massive improvement over ISE for place and route of large designs (30minutes, meets timing, compared with 3hours, fails timing), and the device view is fantastic, I haven't seen any evidence of less need to direct specifics. In fact, it seems to need a little bit more effort. For instance, Vivado infers a clock relationship between unrelated clocks and then fails timing, unless the clocks are explicitly declared to be independent.

For IO, packing registers into the IO blocks should surely be the default behaviour. It's certainly a lot easier than messing around with constraints to try to limit the clock to out delay.

 

One final point regarding HLS :

My experience with VHDL, for a large Virtex 7 design (a quite sophisticated modem) :

coding time = 15% of effort

functional debugging = 15% of effort

Fiddling with the tools and constraints get timing met, registers in IO blocks, high fanout signals duplicated, false paths ignored etc. etc.  = 70% of effort

 

Given this, the idea that adding an extra level of abstraction and complex software between the code and the design will reduce design effort is, well, implausible.

 

Regards,

 David

 

Xilinx Employee
Xilinx Employee
21,363 Views
Registered: ‎07-01-2008

Re: set_property IOB

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Here are examples of setting IOB attributes in Vivado by tracing from the port name through IBUF/OBUF cells to the register cells. I've confirmed that these work. For the output side I had to filter on primitive type because there was an OBUFT involved with a LUT driving the tristate enable and I wanted to avoid putting an IOB property on the LUT.

 

# Input Register

set_attr IOB TRUE [get_cells -of [get_pins -filter {direction=~in} -leaf -of [get_nets -of [get_pins -filter {direction=~out} -of [get_cells -of [get_pins -of [get_nets -of [get_ports input_port_name]]]]]]]]

 

# Output Register

set_attr IOB TRUE [get_cells -filter {PRIMITIVE_GROUP=~FLOP_LATCH} -of [get_pins -filter {direction=~out} -leaf -of [get_nets -of [get_pins -filter {direction=~in} -of [get_cells -of [get_pins -of [get_nets -of [get_ports output_port_name]]]]]]]]

21,216 Views
Registered: ‎04-02-2013

Re: set_property IOB

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I am relatively new to Xilinx and to vivado, but most answers I have read are way to complicated for users. It would be great if vivado supports the XDC syntax as described in UG912: set_property IOB value [get_ports port_name]. My opinion is relying on generated FF names which have to be looked up in the implementation view or searched with complicated TCL scripts is a bad idea (that's at least my opinion). I would like to ask the vivado developers get a decent user-friendly solution for this, not the work-arounds as described above.

Xilinx Employee
Xilinx Employee
21,212 Views
Registered: ‎07-01-2008

Re: set_property IOB

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It appears that 2013.1 now supports the get_ports syntax documented in UG912. I haven't tried it yet, but the Product Requirement (PR 672010) has been closed as verified.

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Scholar pedro_uno
Scholar
20,410 Views
Registered: ‎02-12-2013

Re: set_property IOB

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David,

 

Thank you for your coments.  I agree with your complaints. 

 

In addition to what you say I would offer that for compiling small subdesigns Vivado is much, much slower than ISE.  I have also completed a number of very large FPGA designs.  I find I compile the small subdesigns hundreds of times for each time I actually compile the full chip design. The slowness of Vivado and the way it requires so much clicking, waiting and fiddling really detracts from the optimization I am trying to accomplish by compiling the subdesigns.  I would really rather not write tcl scripts for all these little subdesigns.

 

Anyway, getting back to the orinal thread, I have found that these commands work to force inputs and outputs into the IOB registers of the FPGA.  The old ISE option to default I/O to pack into IOB registers does not exist in Vivado.  I had to click around in the Device View to find the name of my registers and then use these XDC commands on those registers explicitly.

 

# This forces some input registers to pack into the IOB. 
set_property IOB TRUE [get_cells {sink_data_in_reg_reg[*]}]

 

# This forces some output registers to pack into the IOB.
set_property IOB TRUE [get_cells {source_data_out_reg[*]}]

 

 

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Xilinx Employee
Xilinx Employee
28,354 Views
Registered: ‎09-20-2012

Re: set_property IOB

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Hi,

 

You can use the below commands in vivado 2013.x for setting the IOB property to TRUE on all Input and output ports in the design.

 

set_property IOB TRUE [all_inputs]
set_property IOB TRUE [all_outputs]

 

Thanks,

Deepika.

Thanks,
Deepika.
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Scholar pedro_uno
Scholar
20,402 Views
Registered: ‎02-12-2013

Re: set_property IOB

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I have found that these command examples actually work for tracing back from the I/O ports to the associated registers.

 

# This traces from some input ports to find the registers you want to go in the ILOGIC block of the FPGA.

set_property IOB true [all_fanin  -only_cells -startpoints_only -flat [get_ports {source_data_out[*]}]]

 

#This does the same but for output ports.  The syntax is different.
set_property IOB true [all_fanout -only_cells -endpoints_only   -flat [get_ports {sink_data_in[*]}]]

 

Deepika, I don't think your example will work because "set_property IOB true" only works on registers, not inputs or outputs.

 

You could use all_inputs and all_outputs with the above traceback commands but you might want to exclude the clock pin itself to avoid warning messages.

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Scholar pedro_uno
Scholar
20,401 Views
Registered: ‎02-12-2013

Re: set_property IOB

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Deepika,

Actually, I tried your suggestion and it seems to do what I want. I don't think it even generated a warning on the "clk" input pin that cannot be registered. I am using Vivado 2013.2.

I don't know if it will work for all cases but I accept your simple answer as the solution.

Thanks,

Pete
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Xilinx Employee
Xilinx Employee
20,396 Views
Registered: ‎09-20-2012

Re: set_property IOB

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Hi,

To add, the IOB property can be applied on ports also from vivado 2013.1.

 

If you want the IOB property not to be TRUE for some specific ports like CLK then the below can be used.

 

set_property IOB TRUE [all_inputs]

set_property IOB TRUE [all_outputs]

set_property IOB FALSE [get_ports CLK]

 

This applied the IOB property as TRUE on all ports except CLK.


Thanks,
Deepika.

Thanks,
Deepika.
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Visitor emcalnan
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Registered: ‎12-15-2014

Re: set_property IOB

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I have spent over 4 days iterating on a simple design in which I attempt to place the final FF in the IOB.  I have yet to find a constraint that works consistently except for the all_inputs/all_outputs example shown above.  The problem with this example are the hundreds of critical warning issued on the FFs that don't fit into IOBs.

 

One thing I found out early on was the need to put the dont_touch constraint on the FFs that are destined to be fit into the IOBs.  In my simple example I assign a walking one pattern to a set of 48-bit buses.  The synthesis tool will optimize out these FFs unless a dont_touch attribute is assigned because the same test pattern is assigned to all of them.

 

// Keep these from being optimized out due to resource sharing
(* dont_touch = "true" *) reg [47:0] j02_out;
(* dont_touch = "true" *) reg [47:0] j13_out;
(* dont_touch = "true" *) reg [47:0] j14_out;
(* dont_touch = "true" *) reg [47:0] j21_out;
(* dont_touch = "true" *) reg [47:0] j23_out;
(* dont_touch = "true" *) reg [47:0] j22_in;

 

After that I have tried the following - one at a time  - without success.

 

set_property IOB TRUE [get_cells {j02_out*}]

set_property IOB TRUE [get_ports {j02_*}]

 

I also tried several of the examples shown in this thread without success.

 

The following works but emits hundreds of warnings on my little test design:

 

set_property IOB TRUE [all_inputs]

set_property IOB TRUE [all_outputs]

 

I have yet to find a Vivado report file that will indicate whether the register was placed in the IOB - similar to the report file generated by ISE.  In order to determine if the register was placed in the IOB I need to look at the datasheet report generated by the static timing analysis tool and infer the use of an IOB FF from the very consistent clock to out times across my 48-bit buses.

 

Has anyone figured out how to generate a report file that shows which IOs have an IOB FF?

Has anyone figured out in the past 18 months how to consistently place a FF in an IOB without generating a critical warning for every FF upstream of the final FF?

 

Thanks!

 

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Visitor emcalnan
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Registered: ‎12-15-2014

Re: set_property IOB

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I retract what I said about the following constraints:

set_property IOB TRUE [all_inputs]
set_property IOB TRUE [all_outputs]

Even these fail to cause the FFs to be fit into IOBs from route to route. I am at a complete loss as working with a highly utilized XC7V2000T will mean only one iteration/day and my inter-FPGA buses will not meet timing unless the FFs are located in the IOB.
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Participant mtgavin
Participant
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Registered: ‎11-09-2012

Re: set_property IOB

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Hello -

 

I see this post hasn't been updated since February and thought I'd resurrect it.

 

We are now on Vivado 2015.2 and still Vivado seems to fail with: (as per my own experience with my project)

 

- won't infer IOB flops without the user manually setting IOB TRUE in an XDC property (note: ISE didn't need any extra properties set by the user, it did it automatically as guided by timing constraints.)

- generates a critical warning for I/O that don't pack, if you splat the IOB TRUE property across [all_inpus] [all_outputs]  (couldnt this just be a regular, non-critical warning?)

- doesnt have an "IOB REG" column in the IO utilization report , to help the user figure out if the IOB reg is used for that pin (note: ISE had this column in its pad report)

 

I really struggle with why Vivado is SIGNIFICANTLY LESS FUNCTIONAL THAN ISE in this critical area of FPGA design.

 

Can we get this fixed soon? Please?

 

Matt

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Explorer
Explorer
7,590 Views
Registered: ‎12-01-2010

Re: set_property IOB

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I am currently using Vivado 2016.1, and i was having the same IOB implementation issues as many in this thread. My post addresses data inputs only, NOT clock inputs.

The general problem with setting the IOB is that one does not necessarily know what the Synthesized register name is, as it may get changed. Hence the tips on using the TCL commands.
The key is that you want to ensure the correct register name/s BEFORE testing it through a time consuming Synthesis or even Implementation.

So open up your base Synthesized design. Select the Tcl Console tab on the bottom.
And now try the "get_cells" command. If the cell exists, it will return the cell name. If not, you'll get a Warning. You can use the Synthesized schematic to narrow down to what the cell name ended up being, or you can scroll through the Synthesized Netlist hierarchy.

get_cells First_Input_Register_reg 

Tip: If the register (cell) you are looking for isn't there, try setting a "DONT_TOUCH" constraint; it may have been optimized out during Synthesis.

attribute dont_touch : string;
attribute dont_touch of First_Input_Register :signal is "true";

Once the TCL command returns a valid cell, you can then add a line to your .XDC constraints file.

set_property IOB TRUE [get_cells First_Input_Register_reg]

For differential input signals (P,N), you can target the first register, just like above. Alternately, you can target the PORT for the P side of the IBUFDS.

set_property IOB TRUE [get_ports Channel_Data_P]

Finally, run Synthesis and Implementation.  If your signals were checked via TCL, Vivado should have generated no warnings or errors in regards to your constrained IOBs.  You can verify that IOBs were properly implemented by checking the signals with the layout tool (Implemented design).  Just follow a given signal's input pad to the adjacent IOB block.

Good luck!

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Visitor kbeld
Visitor
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Registered: ‎10-22-2016

Re: set_property IOB

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I'm using Vivado 2016.2 and the set_property IOB TRUE [get_cells <cell_name>] constraint still doesn't work.

I can paste the command into the Tcl console and no error messages is given. The commands are all excepted so they are correct.

When I implement the design the last register is not placed in the IOB. The register is just a plain FDRE register without the use of the CE or R inputs. Why is Vivado still not working properly with this constraint?

 

Another very annoying thing. After I pasted the commands in the Tcl console and saved the design the constraints were moved to the bottom of the file and my original constraints including the comments were removed. Surely if the tool sees that the commands already exist [it knows because it removed them] it should leave the constraints alone.

I like to group constraints so I can easily find them back but Vivado makes a mess of my XDC files if I let it make changes.

 

 

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Visitor kbeld
Visitor
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Registered: ‎10-22-2016

Re: set_property IOB

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Oh and the IOB attribute in the RTL is ignored too.
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Visitor kbeld
Visitor
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Registered: ‎10-22-2016

Re: set_property IOB

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Update: the command does work in 2016.2 . You have to select the register and when you open properties it is shown as OUTFF. You can see it in the device layout too. But the schematic doesn't show that the register is placed in the IOB.

I would like to see an easier way, for instance in the IO report, that a register is placed in the IOB. Now you must go into the implementation and look for each of the I/O signals. A column in the IO report like in ISE would be so much easier.
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Participant marco@ms
Participant
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Registered: ‎02-24-2016

Re: set_property IOB

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Did you read this post? https://www.xilinx.com/support/answers/62661.html

It explains how to check if a register is placed in IOB

I hope it helps

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